M30280FCHP#U5B Renesas Electronics America, M30280FCHP#U5B Datasheet - Page 235

• Manufacturer Part Number: M30280FCHP#U5B
• Description: IC M16C/28 MCU FLASH 128K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280FCHP#U5B

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M
R
R
1
e
E
Figure 14.36 S3C and S4C Registers, S3BRG and S4BRG Registers, and S3TRR and S4TRR Registers
. v
6
J
0
C
2
9
2 /
0 .
B
8
0
0
NOTES:
NOTES:
S I / O i T r a n s m i t / r e c e i v e R e g i s t e r ( i = 3 , 4 )
SI/Oi Bit Rate Generator (i=3,4)
NOTES:
0
S I / O i c o n t r o l R e g i s t e r ( i = 3 , 4 )
b 7
b7
G
b 7
4
J
1. Set the S4C register by the next instruction after setting the PRC2 bit in the PRCR register to
2. Set the SMi3 bit to “1” and the corresponding port direction bit to “0”(input mode).
3. Set the SMi3 bit to “1” (S
4. When the SMi2 bit is set to "1", the corresponding pin goes to high-impedance regardless of the function in
5. When the SMi1 and SMi0 bit settings are changed, set the SiBRG register.
7
1. Write to this register while serial I/O is neither transmitting or receiving.
2. Use MOV instruction to write to this regisgter.
3. Set the SiBRG register after setting the SMi1 and SMi0 bits in the SiC register.
a
o r
1. Write to this register while serial I/O is neither transmitting or receiving.
2. To receive data, set the corresponding port direction bit for S
0 -
. n
b 6
use.
u
“1”(write enable).
2
p
3
0
b 5
, 1
0
(
M
2
b 4
1
0
6
0
b3
7
C
2 /
b 2
, 8
page 213
b 1
M
b 0
b 0
b0
1
6
C
A s s u m i n g t h a t s e t v a l u e = n , B R G i d i v i d e s t h e c o u n t s o u r c e
b y n + 1
Transmission/reception starts by writing transmit data to this register. After
transmission/reception finishes, reception data can be read by reading this register.
S y m b o l
OUT
2 /
SMi0
SMi1
S M i 2
S M i 3
S M i 4
SMi5
SMi6
SMi7
f o
B i t
8
i output, CLKi function).
3
) B
8
5
S y m b o l
S 3 C
S 4 C
I n t e r n a l s y n c h r o n o u s c l o c k
s e l e c t b i t
( 1 )
S
S I / O i p o r t s e l e c t b i t
C L K p o l a r i t y s e l c t b i t
T r a n s f e r d i r e c t i o n s e l e c t b i t
S y n c h r o n o u s c l o c k s e l e c t b i t
S
O U T
OUT
Symbol
S3BRG
S4BRG
Symbol
S3TRR
S4TRR
(1, 2, 3)
i o u t p u t d i s a b l e b i t
i initial value set bit
B i t N a m e
(5)
D e s c r i p t i o n
( 1 , 2 )
(4)
Description
A d d r e s s
0 3 6 2
0 3 6 6
Address
0360
0364
Address
0363
0367
IN
b 1 b 0
0 0 : S e l e c t i n g f
0 1 : S e l e c t i n g f
1 0 : S e l e c t i n g f
1 1 : D o n o t s e t
0 : S
1 : S
0 : I n p u t / o u t p u t p o r t
1 : S
0 : T r a n s m i t d a t a i s o u t p u t a t f a l l i n g e d g e o f
1 : T r a n s m i t d a t a i s o u t p u t a t r i s i n g e d g e o f
0 : L S B f i r s t
1 : M S B f i r s t
0 : E x t e r n a l c l o c k
1 : I n t e r n a l c l o c k
Effective when the SMi3 is set to "0"
0 : “L” output
1 : “H” output
1 6
1 6
16
16
16
16
i ti “0”(input mode).
t r a n s f e r c l o c k a n d r e c e i v e d a t a i s i n p u t a t
r i s i n g e d g e
t r a n s f e r c l o c k a n d r e c e i v e d a t a i s i n p u t a t
f a l l i n g e d g e
O U T
O U T
O U T
i o u t p u t
i o u t p u t d i s a b l e ( h i g h i m p e d a n c e )
i o u t p u t , C L K i f u n c t i o n
1
8
3 2
Description
o r f
( 3 )
( 2 )
After Reset
Indeterminate
Indeterminate
A f t e r R e s e t
0 1 0 0 0 0 0 0
0 1 0 0 0 0 0 0
After Reset
Indeterminate
Indeterminate
2
S e t t i n g R a n g e
00
16
2
2
to FF
16
R W
R W
R W
R W
R W
R W
R W
R W
RW
R W
R W
R W
WO
14. Serial I/O