DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 199

IC H8S/2268 MCU FLASH 100QFP

DF2268FA13V

Manufacturer Part Number
DF2268FA13V
Description
IC H8S/2268 MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheets

Specifications of DF2268FA13V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
13MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
LCD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2268FA13V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Note: * Determined by the states of pins P17 to P10.
9.1.4
Port 1 pins also function as TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD * , TIOCA0 * ,
TIOCB0 * , TIOCC0 * , TIOCD0 * , TIOCA1, TIOCB1, TIOCA2, and TIOCB2) and external
interrupt input pins (IRQ0 and IRQ1). Port 1 pin functions are shown below. For the setting of the
TPU channel, see section 10, 16-Bit Timer Pulse Unit (TPU).
Note: * Supported only by the H8S/2268 Group.
• P17/TIOCB2/TCLKD *
Notes: 1. This pin functions as TIOCB2 input when TPU channel 2 timer operating mode is set to
Bit
7
6
5
4
3
2
1
0
TPU Channel 2 Setting
P17DDR
Pin function
The pin function is switched as shown below according to the combination of the TPU channel
2 setting, TPSC2 to TPS0 bits in TCR0 * , and the P17DDR bit.
2. In the H8S/2268 Group, this pin functions as TCLKD input when TPSC2 to TPSC0 in
3. Supported only by the H8S/2268 Group.
Bit Name
P17
P16
P15
P14
P13
P12
P11
P10
Pin Functions
normal operation or phase counting mode *
TCR0 are set to 111 or when channel 2 is set to phase counting mode *
Initial
Value
⎯*
⎯*
⎯*
⎯*
⎯*
⎯*
⎯*
⎯*
3
R/W
R
R
R
R
R
R
R
R
TIOCB2 output
Output
Description
If a port 1 read is performed while P1DDR bits are set to
1, the P1DR values are read. If a port 1 read is performed
while P1DDR bits are cleared to 0, the pin states are
read.
3
and IOB3 in TIOR_2 is set to 1.
TCLKD input *
Rev. 5.00 Sep. 01, 2009 Page 147 of 656
P17 input
0
Input or Initial Value
TIOCB2 input *
2
*
3
Section 9 I/O Ports
REJ09B0071-0500
P17 output
3
.
1
1

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