DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 479
DF2268FA13V
Manufacturer Part Number
DF2268FA13V
Description
IC H8S/2268 MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Specifications of DF2268FA13V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
13MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
LCD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2268FA13V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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14.4.9
The logic levels at the SCL and SDA pins are routed through noise cancellors before being latched
internally. Figure 14.20 shows a block diagram of the noise cancelled circuit.
The noise cancellor consists of two cascaded latches and a match detector. The SCL (or SDA)
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
14.4.10 Initialization of Internal State
The IIC has a function for forcible initialization of its internal state if a deadlock occurs during
communication.
Initialization is executed by (1) setting bits CLR3 to CLR0 in the DDCSWR register or (2)
clearing the ICE bit. For details of settings for bits CLR3 to CLR0, see section 14.3.8, DDC
Switch Register (DDCSWR).
Scope of Initialization: The initialization executed by this function covers the following items:
• TDRE and RDRF internal flags
• Transmit/receive sequencer and internal operating clock counter
• Internal latches for retaining the output state of the SCL and SDA pins (wait, clock, data
output, etc.)
Noise Canceler
SCL or
SDA input
signal
Sampling
clock
Section 14 I
Figure 14.20 Block Diagram of Noise Cancellor
D
Sampling clock
System clock
period
Latch
C
2
C Bus Interface (IIC) (Supported as an Option by H8S/2264 Group)
Q
D
Latch
C
Q
Rev. 5.00 Sep. 01, 2009 Page 427 of 656
detector
Match
REJ09B0071-0500
Internal
SCL or
SDA
signal
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