DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 412

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Sep. 01, 2009 Page 360 of 656
REJ09B0071-0500
[3]
No
No
Read receive data in RDR, and
clear RDRF flag in SSR to 0
Clear ORER flag in SSR to 0
Read ORER flag in SSR
Read RDRF flag in SSR
Clear RE bit in SCR to 0
Overrun error processing
All data received?
Figure 13.22 Sample Serial Reception Flowchart
Error processing
Start reception
Initialization
ORER = 1
RDRF = 1
<End>
<End>
Yes
Yes
No
(Continued below)
Error processing
Yes
[2]
[1]
[3]
[4]
[5]
[1] SCI initialization:
[2] [3] Receive error processing:
[4] SCI status check and receive data
[5] Serial reception continuation
Note: * The case, in which the DTC
The RxD pin is automatically
designated as the receive data input
pin.
If a receive error occurs, read the
ORER flag in SSR, and after
performing the appropriate error
processing, clear the ORER flag to 0.
Transfer cannot be resumed if the
ORER flag is set to 1.
read:
Read SSR and check that the RDRF
flag is set to 1, then read the receive
data in RDR and clear the RDRF flag
to 0.
Transition of the RDRF flag from 0 to 1
can also be identified by an RXI
interrupt.
procedure:
To continue serial reception, before
the final bit of the current frame is
received, reading the RDRF flag,
reading RDR, and clearing the RDRF
flag to 0 should be finished. The
RDRF flag is cleared automatically
when the DTC * is activated by a
receive data full interrupt (RXI) request
and the RDR value is read. (H8S/2268
Group only)
automatically clears the RDRF
flag, occurs only when DISEL in
DTC is 0 with the transfer counter
not being 0. Therefore, the RDRF
flag should be cleared by CPU
when DISEL is 1, or when DISEL
is 0 with the transfer counter
being 0.