DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 50

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Table 10.23 Up/Down-Count Conditions in Phase Counting Mode 4 ....................................... 237
Table 10.24 TPU Interrupts........................................................................................................ 238
Section 11 8-Bit Timers
Table 11.1
Table 11.2
Table 11.3
Table 11.4
Section 12 Watchdog Timer (WDT)
Table 12.1
Section 13 Serial Communication Interface (SCI)
Table 13.1
Table 13.2
Table 13.3
Table 13.3
Table 13.3
Table 13.3
Table 13.4
Table 13.5
Table 13.6
Table 13.7
Table 13.8
Table 13.9
Table 13.10 Serial Transfer Formats (Asynchronous Mode) ..................................................... 339
Table 13.11 SSR Status Flags and Receive Data Handling........................................................ 346
Table 13.12 Interrupt Sources of Serial Communication Interface Mode.................................. 375
Table 13.13 Interrupt Sources in Smart Card Interface Mode.................................................... 376
Section 14 I
Table 14.1
Table 14.2
Table 14.3
Table 14.4
Table 14.5
Table 14.6
Table 14.7
Table 14.8
Rev. 5.00 Sep. 01, 2009 Page xlviii of l
REJ09B0071-0500
Pin Configuration ................................................................................................... 259
8-Bit Timer Interrupt Sources ................................................................................ 274
Timer Output Priorities .......................................................................................... 277
Switching of Internal Clock and TCNT Operation................................................. 278
WDT Interrupt Source............................................................................................ 299
Pin Configuration ................................................................................................... 307
The Relationships between the N Setting in BRR and Bit Rate B ......................... 326
BRR Settings for Various Bit Rates (Asynchronous Mode) (1)............................. 327
BRR Settings for Various Bit Rates (Asynchronous Mode) (2)............................. 328
BRR Settings for Various Bit Rates (Asynchronous Mode) (3)............................. 329
BRR Settings for Various Bit Rates (Asynchronous Mode) (4)............................. 330
Maximum Bit Rate for Each Frequency (Asynchronous Mode) ............................ 330
Maximum Bit Rate with External Clock Input (Asynchronous Mode).................. 331
BRR Settings for Various Bit Rates (Clocked Synchronous Mode) ...................... 332
Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)...... 332
Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode)
(When n = 0 and S = 372) ...................................................................................... 333
Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode)
(When S = 372) ...................................................................................................... 333
Pin Configuration ................................................................................................... 386
Transfer Format...................................................................................................... 391
I
Flags and Transfer States ....................................................................................... 400
Flags and Transfer States ....................................................................................... 426
IIC Interrupt Source ............................................................................................... 429
I
Permissible SCL Rise Time (t
2
2
C Transfer Rate .................................................................................................... 393
C Bus Timing (SCL and SDA Output) ................................................................ 430
2
C Bus Interface (IIC) (Supported as an Option by H8S/2264 Group)
sr
) Values ................................................................. 431