DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 362

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Sep. 01, 2009 Page 310 of 656
REJ09B0071-0500
Bit
4
3
2
1
0
Bit Name
O/E
STOP
MP
CKS1
CKS0
Initial
Value
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Description
Parity Mode (enabled only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity.
1: Selects odd parity.
Stop Bit Length (enabled only in asynchronous mode)
Selects the stop bit length in transmission.
0: 1 stop bit
1: 2 stop bits
In reception, only the first stop bit is checked. If the
second stop bit is 0, it is treated as the start bit of the next
transmit character.
Multiprocessor Mode (enabled only in asynchronous
mode)
When this bit is set to 1, the multiprocessor
communication function is enabled. The PE bit and O/E
bit settings are invalid in multiprocessor mode.
For details, see 13.5, Multiprocessor Communication
Function.
Clock Select 0 and 1
These bits select the clock source for the baud rate
generator.
00: φ clock (n = 0)
01: φ/4 clock (n = 1)
10: φ/16 clock (n = 2)
11: φ/64 clock (n = 3)
For the relationship between the bit rate register setting
and the baud rate, see section 13.3.9, Bit Rate Register
(BRR). n is the decimal representation of the value of n in
BRR (see section 13.3.9, Bit Rate Register (BRR)).
When even parity is set, parity bit addition is
performed in transmission so that the total number of 1
bits in the transmit character plus the parity bit is even.
In reception, a check is performed to see if the total
number of 1 bits in the receive character plus parity bit
is even.
When odd parity is set, parity bit addition is performed
in transmission so that the total number of 1 bits in the
transmit character plus the parity bit is odd. In
reception, a check is performed to see if the total
number of 1 bits in the receive character plus the
parity bit is odd.