DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 414

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Sep. 01, 2009 Page 362 of 656
REJ09B0071-0500
Figure 13.23 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
Notes: When switching from transmit or receive operation to simultaneous transmit and receive operations, first clear
the TE bit and RE bit to 0, then set both these bits to 1 by one instruction simultaneously.
* The case, in which the DTC automatically clears the TDRE flag or RDRF flag, occurs only when DISEL in
No
No
No
the corresponding DTC transfer is 0 with the transfer counter not being 0. Therefore, the corresponding
flag should be cleared by CPU when DISEL in the corresponding DTC transfer is 1, or when DISEL is 0
with the transfer counter being 0.
Clear TE and RE bits in SCR to 0
Read receive data in RDR, and
Write transmit data to TDR and
Start transmission/reception
clear TDRE flag in SSR to 0
clear RDRF flag in SSR to 0
Read ORER flag in SSR
Read TDRE flag in SSR
Read RDRF flag in SSR
All data received?
Initialization
ORER = 1
TDRE = 1
RDRF = 1
<End>
Yes
Yes
Yes
No
Error processing
Yes
[1]
[2]
[4]
[5]
[3]
[1] SCI initialization:
[2] SCI status check and transmit data
[3] Receive error processing:
[4] SCI status check and receive data
[5] Serial transmission/reception
The TxD pin is designated as the
transmit data output pin, and the RxD
pin is designated as the receive data
input pin, enabling simultaneous
transmit and receive operations.
write:
Read SSR and check that the TDRE
flag is set to 1, then write transmit
data to TDR and clear the TDRE flag
to 0.
Transition of the TDRE flag from 0 to
1 can also be identified by a TXI
interrupt.
If a receive error occurs, read the
ORER flag in SSR, and after
performing the appropriate error
processing, clear the ORER flag to 0.
Transmission/reception cannot be
resumed if the ORER flag is set to 1.
read:
Read SSR and check that the RDRF
flag is set to 1, then read the receive
data in RDR and clear the RDRF flag
to 0. Transition of the RDRF flag from
0 to 1 can also be identified by an RXI
interrupt.
continuation procedure:
To continue serial transmission/
reception, before the final bitof the
current frame is received, finish
reading the RDRF flag, reading RDR,
and clearing the RDRF flag to 0.
Also, before the final bit of the current
frame is transmitted, read 1 from the
TDRE flag to confirm that writing is
possible. Then write data to TDR and
clear the TDRE flag to 0.
Checking and clearing of the TDRE
flag is automatic when the DTC * is
activated by a transmit data empty
interrupt (TXI) request and data is
written to TDR. Also, the RDRF flag
is cleared automatically when the
DTC * is activated by a receive data
full interrupt (RXI) request and the
RDR value is read.
Group only)
(H8S/2268