DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 465

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 14.10 Flowchart for Master Receive Mode (Receiving Multiple Bytes) (WAIT = 1)
No
No
No
Section 14 I
Clear IRIC flag in ICCR
Clear IRIC flag in ICCR
Read IRIC flag in ICCR
Clear IRIC flag in ICCR
Read IRIC flag in ICCR
Clear IRIC flag in ICCR
Clear IRIC flag in ICCR
1 clock cycle wait state
Set ACKB = 0 (ICSR)
Set WAIT = 1 (ICMR)
Set ACKB = 1 (ICSR)
Set WAIT = 0 (ICMR)
Master receive mode
and SCP = 0 (ICCR)
Set TRS = 0 (ICCR)
Set TRS = 1 (ICCR)
Write BBSY = 0
Is next receive
the last one?
Read ICDR
Read ICDR
Read ICDR
Read ICDR
IRTR = 1?
IRTR = 1?
IRIC = 1?
IRIC = 1?
End
Yes
Yes
Yes
No
No
2
C Bus Interface (IIC) (Supported as an Option by H8S/2264 Group)
Yes
Yes
(Example)
[1] Set to receive mode.
[2] Receive start, dummy read.
[3] Receive wait state (IRIC set at falling edge of 8th clock cycle)
[4] Data receive completed judgment.
[5] Read receive data.
[6] Clear IRIC flag (cancel wait state).
[7] Set acknowledge data for final receive.
[8] Wait time until TRS setting.
[9] Set TRS to generate stop condition.
[10] Read receive data.
[11] Clear IRIC flag (cancel wait state).
[12] Receive wait state (IRIC set at falling edge of 8th clock cycle)
[13] Data receive completed judgment.
[14] Clear IRIC flag (cancel wait state).
[15] Cancel wait mode
[16] Read final receive data.
[17] Generate stop condition.
or
Wait for end of reception of 1 byte (IRIC set at rising edge
of 9th clock cycle).
or
Wait for end of reception of 1 byte (IRIC set at rising edge
of 9th clock cycle).
Clear IRIC flag. (IRIC flag should be cleared when WAIT = 0.)
Rev. 5.00 Sep. 01, 2009 Page 413 of 656
REJ09B0071-0500