DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 577

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

20.8.1
When writing data or programs to the flash memory, the program/program-verify flowchart shown
in figure 20.10 should be followed. Performing programming operations according to this
flowchart will enable data or programs to be written to the flash memory without subjecting the
chip to voltage stress or sacrificing program data reliability.
1. Programming must be done to an empty address. Do not reprogram an address to which
2. Programming should be carried out 128 bytes at a time. A 128-byte data transfer must be
3. Prepare the following data storage areas in RAM: A 128-byte programming data area, a 128-
4. Consecutively transfer 128 bytes of data in byte units from the reprogramming data area or
5. The time during which the P1 bit is set to 1 is the programming time. Figure 20.10 shows the
6. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.
7. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 1 bit
8. The maximum number of repetitions of the program/program-verify sequence of the same bit
programming has already been performed.
performed even if writing fewer than 128 bytes. In this case, H'FF data must be written to the
extra addresses.
byte reprogramming data area, and a 128-byte additional-programming data area. Perform
reprogramming data computation and additional programming data computation according to
figure 20.10.
additional-programming data area to the flash memory. The program address and 128-byte
data are latched in the flash memory. The lower 8 bits of the start address in the flash memory
destination area must be H'00 or H'80.
allowable programming times.
Set a value greater than (tspsu + tsp200 + tcp + tcpsu) µs as the WDT overflow period.
is B'0. Verify data can be read in words from the address to which a dummy write was
performed.
is (N).
Program/Program-Verify
Rev. 5.00 Sep. 01, 2009 Page 525 of 656
REJ09B0071-0500
Section 20 ROM