DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 460

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 14 I
14.4.2
At startup the following procedure is used to initialize the IIC.
Note: The ICMR register should be written to only after transmit or receive operations have
14.4.3
In I
data, and the slave device returns an acknowledge signal.
Figure 14.7 is a flowchart showing an example of the master transmit mode.
Rev. 5.00 Sep. 01, 2009 Page 408 of 656
REJ09B0071-0500
2
C bus format master transmit mode, the master device outputs the transmit clock and transmit
completed.
Writing to the ICMR register while a transmit or receive operation is in progress could
cause an erroneous value to be written to bit counter bits BC2 to BC0. This could result in
improper operation.
Master Transmit Operation
Initial Setting
2
C Bus Interface (IIC) (Supported as an Option by H8S/2264 Group)
Set MSTPB4 = 0 (IIC0)
Transmit/receive start
Set IICE = 1 (SCRX)
Set SAR and SARX
MSTPB3 = 0 (IIC1)
Set ICE = 0 (ICCR)
Set ICE = 1 (ICCR)
Start initialization
(MSTPCRB)
Set SCRX
Set ICMR
Figure 14.6 Flowchart for IIC Initialization (Example)
Set ICCR
Set ICSR
Note: Setting only valid for H8S/2268 Group.
Clear module stop.
Enable CPU access by IIC control register and data register.
Enable SAR and SARX access.
Set transfer format for 1st slave address, 2nd slave address,
and IIC (SVA8 to SVA0, FS, SVAX6 to SVAX0, FSX).
Enable IMCR and IMDR access. Use SCL and SDA pins is IIC
port.
Set acknowledge bit (ACKB).
Set transfer rate (IICX).
Set transfer format, wait insertion, and transfer rate (MLS,
WAIT, CKS2 to CKS0).
Set interrupt enable, transfer mode, and acknowledge
judgment (IEIC, MST, TRS, ACKE).
For the H8S/2264 Group, only write 1 to this bit.