DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 347

IC H8S/2268 MCU FLASH 100QFP

DF2268FA13V

Manufacturer Part Number
DF2268FA13V
Description
IC H8S/2268 MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheets

Specifications of DF2268FA13V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
13MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
LCD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2268FA13V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
12.2.3
RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects
the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin,
and not by the WDT internal reset signal caused by overflows.
Note: * Only 0 can be written, to clear the flag.
Bit
7
6
5
4 to 0
Bit Name
WOVF
RSTE
Reset Control/Status Register (RSTCSR) (Only WDT_0)
Initial
Value
0
0
0
All 1
R/W
R/(W) * Watchdog Overflow Flag
R/W
R/W
Description
This bit is set when TCNT overflows in watchdog timer
mode. This bit cannot be set in interval timer mode, and
only 0 can be written, to clear the flag.
[Setting condition]
Set when TCNT overflows (changed from H'FF to H'00) in
watchdog timer mode
[Clearing condition]
Cleared by reading RSTCSR when WOVF = 1, and then
writing 0 to WOVF
Reset Enable
Specifies whether or not a reset signal is generated in the
chip if TCNT overflows during watchdog timer operation.
0: Reset signal is not generated even if TCNT overflows
1: Reset signal is generated if TCNT overflows
Reserved
This bit can be read from and written to. However, the
write value should always be 0.
Reserved
These bits are always read as 1 and cannot be modified.
(Though this LSI is not reset, TCNT and TCSR in WDT
are reset)
Rev. 5.00 Sep. 01, 2009 Page 295 of 656
Section 12 Watchdog Timer (WDT)
REJ09B0071-0500

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