DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 571

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5. In boot mode, a part of the on-chip RAM area is used by the boot program. The area
6. Before branching to the programming control program, the chip terminates transfer operations
7. Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting
8. All interrupts are disabled during programming or erasing of the flash memory.
Note: * The input signals on the FWE and mode pins must satisfy the mode programming setup
the bit rates of the host and the chip. To operate the SCI properly, set the host's transfer bit rate
and system clock frequency of this LSI within the ranges listed in table 20.5.
H'FFC000 to H'FFDFFF is the area to which the programming control program is transferred
from the host. In the H8S/2266 and H8S/2265, the RAM in this area is enabled only in boot
mode. The boot program area cannot be used until the execution state in boot mode switches to
the programming control program.
by SCI_0 (by clearing the RE and TE bits in SCR to 0), however the adjusted bit rate value
remains set in BRR. Therefore, the programming control program can still use it for transfer of
write data or verify data with the host. The TxD pin is high. The contents of the CPU general
registers are undefined immediately after branching to the programming control program.
These registers must be initialized at the beginning of the programming control program, as the
stack pointer (SP), in particular, is used implicitly in subroutine calls, etc.
the FWE pin and mode pins, and executing reset release * . Boot mode is also cleared when a
WDT overflow occurs.
time (t
MDS
= 200 ns) at the reset release timing.
Rev. 5.00 Sep. 01, 2009 Page 519 of 656
REJ09B0071-0500
Section 20 ROM