HD64F3337YCP16 Renesas Electronics America, HD64F3337YCP16 Datasheet - Page 194

• Manufacturer Part Number: HD64F3337YCP16
• Description: IC H8 MCU FLASH 60K 84PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• Package: 84PLCC
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 74
• Interface Type: HIF/I2C/SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

8.2.3
There are four input capture registers A to D, each of which is a 16-bit read-only register.
When the rising or falling edge of the signal at an input capture pin (FTIA to FTID) is detected,
the current FRC value is copied to the corresponding input capture register (ICRA to ICRD).* At
the same time, the corresponding input capture flag (ICFA to ICFD) in the timer control/status
register (TCSR) is set to 1. The input capture edge is selected by the input edge select bits
(IEDGA to IEDGD) in the timer control register (TCR).
Note: * The FRC contents are transferred to the input capture register regardless of the value of the
Input capture can be buffered by using the input capture registers in pairs. When the BUFEA bit in
TCR is set to 1, ICRC is used as a buffer register for ICRA as shown in figure 8.2. When an FTIA
input is received, the old ICRA contents are moved into ICRC, and the new FRC count is copied
into ICRA.
162
BUFEA:
IEDGA:
IEDGC:
ICRC:
ICRA:
FRC:
Bit
Initial value
Read/Write
input capture flag (ICFA/B/C/D).
FTIA
Input Capture Registers A to D (ICRA to ICRD)
Buffer enable A
Input edge select A
Input edge select C
Input capture register C
Input capture register A
Free-running counter
15
R
0
14
R
0
Figure 8.2 Input Capture Buffering (Example)
generating circuit
Edge detect and
IEDGA
capture signal
13
R
0
BUFEA
12
R
0
IEDGC
ICRC
11
R
0
10
R
0
R
9
0
R
8
0
ICRA
R
7
0
R
6
0
R
5
0
R
4
0
R
3
0
FRC
R
2
0
R
1
0
R
0
0