HD64F3337YCP16 Renesas Electronics America, HD64F3337YCP16 Datasheet - Page 89

• Manufacturer Part Number: HD64F3337YCP16
• Description: IC H8 MCU FLASH 60K 84PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• Package: 84PLCC
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 74
• Interface Type: HIF/I2C/SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

2.6.4
The power-down state includes three modes: sleep mode, software standby mode, and hardware
standby mode.
Sleep Mode: Is entered when a SLEEP instruction is executed. The CPU halts, but CPU register
contents remain unchanged and the on-chip supporting modules continue to function.
Software Standby Mode: Is entered if the SLEEP instruction is executed while the SSBY
(Software Standby) bit in the system control register (SYSCR) is set. The CPU and all on-chip
supporting modules halt. The on-chip supporting modules are initialized, but the contents of the
on-chip RAM and CPU registers remain unchanged as long as a specified voltage is supplied. I/O
port outputs also remain unchanged.
Hardware Standby Mode: Is entered when the input at the
functions halt, including I/O port output. The on-chip supporting modules are initialized, but on-
chip RAM contents are held.
See section 22, Power-Down State, for further information.
2.7
The CPU is driven by the system clock (ø). The period from one rising edge of the system clock to
the next is referred to as a “state.” Memory access is performed in a two- or three-state bus cycle.
On-chip memory, on-chip supporting modules, and external devices are accessed in different bus
cycles as described below.
2.7.1
On-chip ROM and RAM are accessed in a cycle of two states designated T
word data can be accessed, via a 16-bit data bus. Figure 2.13 shows the on-chip memory access
cycle. Figure 2.14 shows the associated pin states.
Power-Down State
Access Timing and Bus Cycle
Access to On-Chip Memory (RAM and ROM)
STBY
pin goes low. All chip
1
and T
2
. Either byte or
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