HD64F3337YCP16 Renesas Electronics America, HD64F3337YCP16 Datasheet - Page 353

• Manufacturer Part Number: HD64F3337YCP16
• Description: IC H8 MCU FLASH 60K 84PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• Package: 84PLCC
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 74
• Interface Type: HIF/I2C/SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

14.2.4
Bit
Initial value
Slave Read/Write
Host Read/Write
ODR1 is an 8-bit read/write register to the slave processor, and an 8-bit read-only register to the
host processor. The ODR1 contents are output on the host data bus when HA
and
The initial values of ODR1 after a reset or standby are undetermined.
14.2.5
Bit
Initial value
Slave Read/Write
Host Read/Write
STR1 is an 8-bit register that indicates status information during host interface processing. Bits 3,
1, and 0 are read-only bits to both the host and slave processors.
STR1 is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 to 4 and Bit 2—Defined by User (DBU): The user can use these bits as necessary.
Bit 3—Command/Data (C/D): Receives the HA
and indicates whether IDR1 contains data or a command.
Bit 3: C/D
0
1
IOR
is low.
Output Data Register 1 (ODR1)
Status Register 1 (STR1)
ODR7
Description
Contents of IDR1 are data
Contents of IDR1 are a command
DBU
R/W
R/W
—
R
R
7
7
0
ODR6
DBU
R/W
R/W
—
R
R
6
6
0
ODR5
DBU
R/W
R/W
—
R
R
5
5
0
0
ODR4
input when the host processor writes to IDR1,
DBU
R/W
R/W
—
R
R
4
4
0
ODR3
R/W
C/D
—
R
R
R
3
3
0
ODR2
DBU
R/W
R/W
—
R
R
2
2
0
0
is low,
ODR1
R/W
IBF
—
R
R
R
1
1
0
CS
(Initial value)
1
is low,
ODR0
OBF
R/W
—
R
R
R
0
0
0
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