HD64F3337YCP16 Renesas Electronics America, HD64F3337YCP16 Datasheet - Page 64

• Manufacturer Part Number: HD64F3337YCP16
• Description: IC H8 MCU FLASH 60K 84PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• Package: 84PLCC
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 74
• Interface Type: HIF/I2C/SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

2.4
2.4.1
The H8/300 CPU supports eight addressing modes. Each instruction uses a subset of these
addressing modes.
Table 2.1
No.
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(1) Register Direct—Rn: The register field of the instruction specifies an 8- or 16-bit general
register containing the operand. In most cases the general register is accessed as an 8-bit register.
Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits
DIVXU (16 bits 8 bits) instructions have 16-bit operands.
(2) Register Indirect—@Rn: The register field of the instruction specifies a 16-bit general
register containing the address of the operand.
(3) Register Indirect with Displacement—@(d:16, Rn): This mode, which is used only in
MOV instructions, is similar to register indirect but the instruction has a second word (bytes 3 and
4) which is added to the contents of the specified general register to obtain the operand address.
For the MOV.W instruction, the resulting address must be even.
(4) Register Indirect with Post-Increment or Pre-Decrement—@Rn+ or @–Rn:
32
Register indirect with Post-Increment—@Rn+
The @Rn+ mode is used with MOV instructions that load registers from memory.
It is similar to the register indirect mode, but the 16-bit general register specified in the register
field of the instruction is incremented after the operand is accessed. The size of the increment
is 1 or 2 depending on the size of the operand: 1 for MOV.B; 2 for MOV.W. For MOV.W, the
original contents of the 16-bit general register must be even.
Addressing Modes
Addressing Mode
Addressing Mode
Register direct
Register indirect
Register indirect with displacement
Register indirect with post-increment
Register indirect with pre-decrement
Absolute address
Immediate
Program-counter-relative
Memory indirect
Addressing Modes
Symbol
Rn
@Rn
@(d:16, Rn)
@Rn+
@–Rn
@aa:8 or @aa:16
#xx:8 or #xx:16
@(d:8, PC)
@@aa:8
8 bits), and