HD64F3337YCP16 Renesas Electronics America, HD64F3337YCP16 Datasheet - Page 327

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HD64F3337YCP16

Manufacturer Part Number
HD64F3337YCP16
Description
IC H8 MCU FLASH 60K 84PLCC
Manufacturer
Renesas Electronics America
Series
H8® H8/300r
Datasheets

Specifications of HD64F3337YCP16

Core Processor
H8/300
Core Size
8-Bit
Speed
16MHz
Connectivity
Host Interface, I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
84-PLCC
Package
84PLCC
Family Name
H8
Maximum Speed
16 MHz
Operating Supply Voltage
5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
74
Interface Type
HIF/I2C/SCI
On-chip Adc
8-chx10-bit
On-chip Dac
2-chx8-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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13.3
13.3.1
The I
figure 13.3, and a non-addressing format, shown as (c) in figure 13.4. The first byte following a
start condition always consists of 8 bits. Figure 13.5 shows the I
Legend:
S:
SLA:
R/W:
A:
(a) Addressing format (FS = 0)
(b) Addressing format (retransmit start condition, FS = 0)
S
S
1
1
(c) Non-addressing format (FS = 1)
2
C bus interface has three data formats: two addressing formats, shown as (a) and (b) in
S
1
Operation
I
Start condition. The master device drives SDA from high to low while SCL is high.
Slave address, by which the master device selects a slave device.
Indicates the direction of data transfer: from the slave device to the master device when
R/W is 1, or from the master device to the slave device when R/W is 0.
Acknowledge. The receiving device (the slave in master transmit mode, or the master in
master receive mode) drives SDA low to acknowledge a transfer. If transfers need not be
SLA
SLA
2
7
7
C Bus Data Format
DATA
Figure 13.4 I
1
1
Figure 13.3 I
8
R/W
R/W
1
1
1
A
A
1
1
A
1
2
DATA
DATA
C Bus Data Format (Non-Acknowledge Format)
n1
2
n
C Bus Data Formats (Acknowledge Formats)
DATA
m1
n
A
1
A/A
m
1
A
1
S
1
m
n1 and n2: bit count (n1 and n2 = 1 to 8)
m1 and m2: frame count (m1 and m2
SLA
A/A
1
7
P
1
1
R/W
2
C bus timing.
1
m: frame count
(m
n: bit count
(n = 1 to 8)
A/A
1
1)
A
1
P
1
DATA
n2
m: frame count
(m
n: bit count
(n = 1 to 8)
m2
1)
1)
A/A
1
1
P
295

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