M30835FJGP#U5 Renesas Electronics America, M30835FJGP#U5 Datasheet - Page 133

• Manufacturer Part Number: M30835FJGP#U5
• Description: IC M32C/83 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30835FJGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 121
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
10.11 Intelligent I/O Interrupt and CAN Interrupt
e
E
3
. v
J
Figure 10.13 Intelligent I/O Interrupt and CAN Interrupt
2
0
The intelligent I/O interrupt and CAN interrupt are assigned to software interrupt numbers 44 to 54, and 57.
Figure 10.13 shows a block diagram of the intelligent I/O interrupt and CAN interrupt. Figure 10.14 shows
the IIOiIR register (i = 0 to 11). Figure 10.15 shows the IIOiIE register.
When using the intelligent I/O interrupt or CAN interrupt, set the IRLT bit in the IIOiIE register to "1" (inter-
rupt request for interrupt used).
Various interrupt requests cause the intelligent I/O interrupt to occur. When an interrupt request is gener-
ated with intelligent I/O or CAN functions, the corresponding bit in the IIOiIR register is set to "1" (interrupt
requested). When the corresponding bit in the IIOiIE register is set to "1" (interrupt enabled), the IR bit in
the corresponding IIOiIC register is set to "1" (interrupt requested).
After the IR bit setting changes from "0" to "1", the IR bit remains set to "1" when a bit in the IIOiIR register
is set to "1" by another interrupt request and the corresponding bit in the IIOiIE register is set to "1".
Bits in the IIOiIR register are not set to "0" automatically, even if an interrupt is acknowledged. Set each bit
to "0" by program. If these bits remain set to "1", all generated interrupt requests are ignored.
CAN interrupt uses bit 7 in the IIO9IR to IIO11IR registers and bit 7 in the IIO9IE to IIO11IE registers. IIO9IR
to IIO11IR registers share addresses with the CAN0IC to CAN2IC registers. Refer to 22.3 CAN Interrupt
for details.
When using the intelligent I/O interrupt or CAN interrupt to activate DMAC II, set the IRLT bit in the IIOiIE
register to "0" (an interrupt used for DMAC, DMAC II) to enable the interrupt request that the IIOiIE register
requires.
1
9
C
3 .
Interrupt Request
B
Interrupt Request
Interrupt Request
8 /
0
1
3
0
3
J
G
4
a
0 -
n
o r
3 .
1
u
, 1
3
p
1
2
(
M
0
0
3
(1)
(1)
(1)
6
2
C
IIOiIR Register
8 /
IIOiIE Register
Page 108
, 3
M
Bit 1
Bit 2
Bit 7
Bit 1
Bit 2
Bit 7
3
2
C
f o
8 /
4
(2)
(3)
3
8
) T
8
IRLT Bit in
IIOiIE Register
0
1
0
1
0
1
NOTES:
i= 0 to 11
1. See Figures 10.14 and 10.15 for details on bits 1 to 7 in
2. Bits 1 to 7 in the IIOiIR register are not set to "0"
3. Do not change the IRLT bit and the interrupt enable bit in
the IIOiIR register and bits 1 to 7 in the IIOiIE register.
automatically even if an interrupt request is generated.
Set to "0" by program.
the IIOiIE register simultaneously.
Intelligent I/O Interrupt i Request
10. Interrupts