M30835FJGP#U5 Renesas Electronics America, M30835FJGP#U5 Datasheet - Page 147

• Manufacturer Part Number: M30835FJGP#U5
• Description: IC M32C/83 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30835FJGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 121
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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Figure 12.6 Transfer Cycle Examples with the Source-Read Bus Cycle
0
2
1
9
C
3 .
B
8 /
0
1
0
3
3
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G
4
a
0 -
n
o r
3 .
1
(1) When 8-bit data is transferred
(3) When one wait state is inserted into the source-read bus cycle under the conditions in (1)
(2) When 16-bit data is transferred from an odd source address
u
(4) When one wait state is inserted into the source-read bus cycle under the conditions in (2)
, 1
3
WR Signal
RD Signal
BCLK
NOTES:
p
WR Signal
BCLK
WR Signal
Address
Bus
Data
Bus
WR Signal
BCLK
Address
Bus
RD Signal
Data
bus
CPU Clock
Address
Bus
RD Signal
Data
Bus
BCLK
Address
Bus
RD Signal
Data
Bus
1
or when 16-bit data is transferred from an even source address by a 16-bit data bus
2
or when 16-bit data is transferred from source by an 8-bit data bus
(
1. The above applies when the destination-write bus cycle is 2 BCLK cycles (1 bus cycle).
0
M
0
However, if the destination-write bus cycle is placed under these conditions, it will change to
the same timing as the source-read bus cycle illustrated above.
3
6
2
C
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8 /
, 3
CPU Use
CPU Use
CPU Use
M
CPU Use
CPU Use
CPU Use
CPU Use
CPU Use
3
2
C
f o
8 /
4
8
3
8
) T
Source
Source
Source
Source
Source
Source
Source + 1
Source
Source
Destination
Source + 1
Destination
Destination
Destination
Source + 1
Destination
Source + 1
Destination
Destination
CPU Use
CPU Use
Destination
CPU Use
CPU Use
CPU Use
CPU Use
CPU Use
CPU Use
12. DMAC