M30835FJGP#U5 Renesas Electronics America, M30835FJGP#U5 Datasheet - Page 231

• Manufacturer Part Number: M30835FJGP#U5
• Description: IC M32C/83 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30835FJGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 121
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
. v
3
J
Table 16.21 Pin Settings in Special Mode 2 (1)
Table 16.21 Pin Settings (2)
Table 16.23 Pin Settings (3)
0
2
NOTES:
NOTES:
P6
P6
P6
P6
P6
P6
P6
P6
P7
P7
P7
P7
P9
P9
P9
P9
P9
P9
P9
P9
1
9
C
Port
3 .
B
Port
Port
1. P7
1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do not
8 /
0
1
2
3
4
5
6
7
0 (1)
1 (1)
2
3
0
1
2
3
4
5
6
7
0
1
0
3
generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the instruction to set
the PD9 and PS3 registers.
3
J
G
4
a
0
0 -
n
o r
and P7
TxD2 output (master)
SRxD2 input (slave)
RxD2 input (master)
STxD2 output (slave)
CLK2 input (slave)
CLK2 output (master)
SS2 input
3 .
______
1
u
_______
CLK3 input (slave)
CLK3 output (master)
RxD3 input (master)
STxD3 output (slave)
TxD3 output (master)
SRxD3 input (slave)
SS3 input
SS4 input
CLK4 input (slave)
CLK4 output (master)
TxD4 output (master)
SRxD4 input (slave)
RxD4 input (master)
STxD4 output (slave)
, 1
3
______
p
SS0 input
CLK0 input (slave)
CLK0 output (master)
RxD0 input (master)
STxD0 output (slave)
TxD0 output (master)
SRxD0 input (slave)
SS1 input
CLK1 input (slave)
CLK1 output (master)
RxD1 input (master)
STxD1 output (slave)
TxD1 output (master)
SRxD1 input (slave)
______
______
1
2
(
M
0
Function
1
0
3
Function
6
are ports for the N-channel open drain output.
2
Function
C
Page 206
8 /
, 3
M
3
2
C
f o
8 /
PS1_0=1
PS1_0=0
PS1_1=0
PS1_1=1
PS1_2=0
PS1_2=1
PS1_3=0
4
8
3
PS3_0=0
PS3_0=1
PS3_1=0
PS3_1=1
PS3_2=1
PS3_2=0
PS3_3=0
PS3_4=0
PS3_5=0
PS3_5=1
PS3_6=1
PS3_6=0
PS3_7=0
PS3_7=1
PS1 Register
8
) T
PS0_0=0
PS0_1=0
PS0_1=1
PS0_2=0
PS0_2=1
PS0_3=1
PS0_3=0
PS0_4=0
PS0_5=0
PS0_5=1
PS0_6=0
PS0_6=1
PS0_7=1
PS0_7=0
PS3 Register
PS0 Register
(1)
PSL1_0=0
–
–
PSL1_1=1
–
PSL1_2=0
–
PSL1 Register
–
–
–
PSL3_1=1
PSL3_2=0
–
PSL3_3=0
PSL3_4=0
PSL3_5=0
–
–
PSL3_6=0
–
PSL3_7=1
PSL0_2=1
–
–
–
–
PSL0_6=1
–
–
–
–
–
–
–
–
PSL3 Register
PSL0 Register
Setting
Setting
Setting
PSC_0=0
–
–
PSC_1=0
–
PSC_2=0
–
PSC Register
PD9_0=0
–
PD9_1=0
–
–
PD9_2=0
PD9_3=0
PD9_4=0
PD9_5=0
–
–
PD9_6=0
PD9_7=0
–
PD6_0=0
PD6_1=0
–
PD6_2=0
–
–
PD6_3=0
PD6_4=0
PD6_5=0
–
PD6_6=0
–
–
PD6_7=0
PD9 Register
PD6 Register
16. Serial I/O (Special Function)
(1)
–
PD7_0=0
PD7_1=0
–
PD7_2=0
–
PD7_3=0
PD7 Register