UPD70F3736GK-GAK-AX Renesas Electronics America, UPD70F3736GK-GAK-AX Datasheet - Page 10

• Manufacturer Part Number: UPD70F3736GK-GAK-AX
• Description: MCU 32BIT V850ES/JX3-L 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3736GK-GAK-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 66
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Program Memory Size: 256KB (256K x 8)
• Data Converters: A/D 8x10b, D/A 1x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CHAPTER 5 BUS CONTROL FUNCTION .......................................................................................... 153
CHAPTER 6 CLOCK GENERATION FUNCTION .............................................................................. 175
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) ................................................................ 189
10
4.4
4.5
4.6
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
6.1
6.2
6.3
6.4
6.5
7.1
4.3.10
4.3.11
Block Diagrams..................................................................................................................... 113
Port Register Settings When Alternate Function Is Used ................................................ 141
Cautions ................................................................................................................................ 148
4.6.1
4.6.2
4.6.3
4.6.4
4.6.5
4.6.6
Features................................................................................................................................. 153
Bus Control Pins................................................................................................................... 154
5.2.1
5.2.2
Memory Block Function....................................................................................................... 155
Bus Access ........................................................................................................................... 156
5.4.1
5.4.2
5.4.3
Wait Function ........................................................................................................................ 164
5.5.1
5.5.2
5.5.3
5.5.4
Idle State Insertion Function ............................................................................................... 168
Bus Hold Function................................................................................................................ 169
5.7.1
5.7.2
5.7.3
Bus Priority ........................................................................................................................... 171
Bus Timing ............................................................................................................................ 172
Overview................................................................................................................................ 175
Configuration ........................................................................................................................ 176
Registers ............................................................................................................................... 178
Operation............................................................................................................................... 183
6.4.1
6.4.2
PLL Function......................................................................................................................... 184
6.5.1
6.5.2
6.5.3
Overview................................................................................................................................ 189
Port DH ....................................................................................................................................109
Port DL ....................................................................................................................................110
Cautions on setting port pins ...................................................................................................148
Cautions on bit manipulation instruction for port n register (Pn)...............................................151
Cautions on on-chip debug pins...............................................................................................152
Cautions on P05/INTP2/DRST pin...........................................................................................152
Cautions on P10 and P53 pins when power is turned on.........................................................152
Hysteresis characteristics ........................................................................................................152
Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed...............154
Pin status in each operation mode...........................................................................................154
Number of clocks for access....................................................................................................156
Bus size setting function ..........................................................................................................156
Access by bus size ..................................................................................................................157
Programmable wait function ....................................................................................................164
External wait function...............................................................................................................165
Relationship between programmable wait and external wait ...................................................166
Programmable address wait function.......................................................................................167
Functional outline.....................................................................................................................169
Bus hold procedure..................................................................................................................170
Operation in power save mode ................................................................................................170
Operation of each clock ...........................................................................................................183
Clock output function ...............................................................................................................183
Overview..................................................................................................................................184
Registers..................................................................................................................................184
Usage ......................................................................................................................................188
Preliminary User’s Manual U18952EJ1V0UD