UPD70F3736GK-GAK-AX Renesas Electronics America, UPD70F3736GK-GAK-AX Datasheet - Page 626
UPD70F3736GK-GAK-AX
Manufacturer Part Number
UPD70F3736GK-GAK-AX
Description
MCU 32BIT V850ES/JX3-L 80-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet
1.UPD70F3736GK-GAK-AX.pdf
(830 pages)
Specifications of UPD70F3736GK-GAK-AX
Package / Case
*
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Speed
20MHz
Number Of I /o
66
Core Processor
RISC
Program Memory Type
FLASH
Ram Size
16K x 8
Program Memory Size
256KB (256K x 8)
Data Converters
A/D 8x10b, D/A 1x8b
Oscillator Type
Internal
Peripherals
DMA, LVD, PWM, WDT
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
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Price
Company:
Part Number:
UPD70F3736GK-GAK-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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18.13 Cautions
626
(1) Caution for VSWC register
(2) Caution for DMA transfer executed on internal RAM
(3) Caution for reading DCHCn.TCn bit (n = 0 to 3)
When using the DMAC, be sure to set an appropriate value, in accordance with the operating frequency, to the
VSWC register.
When the default value (77H) of the VSWC register is used, or if an inappropriate value is set to the VSWC
register, the operation is not correctly performed (for details of the VSWC register, see 3.4.8 (1) (a) System
wait control register (VSWC)).
When executing the following instructions located in the internal RAM, do not execute a DMA transfer that
transfers data to/from the internal RAM (transfer source/destination), because the CPU may not operate
correctly afterward.
Conversely, when executing a DMA transfer to transfer data to/from the internal RAM (transfer
source/destination), do not execute the above two instructions.
The TCn bit is cleared to 0 when it is read, but it is not automatically cleared even if it is read at a specific
timing. To accurately clear the TCn bit, add the following processing.
(a) When waiting for completion of DMA transfer by polling TCn bit
(b) When reading TCn bit in interrupt servicing routine
• Bit manipulation instruction located in internal RAM (SET1, CLR1, or NOT1)
• Data access instruction to misaligned address located in internal RAM
Confirm that the TCn bit has been set to 1 (after TCn bit = 1 is read), and then read the TCn bit three more
times.
Execute reading the TCn bit three times.
CHAPTER 18 DMA FUNCTION (DMA CONTROLLER)
Preliminary User’s Manual U18952EJ1V0UD
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