UPD70F3736GK-GAK-AX Renesas Electronics America, UPD70F3736GK-GAK-AX Datasheet - Page 687

• Manufacturer Part Number: UPD70F3736GK-GAK-AX
• Description: MCU 32BIT V850ES/JX3-L 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3736GK-GAK-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 66
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Program Memory Size: 256KB (256K x 8)
• Data Converters: A/D 8x10b, D/A 1x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

21.6.2 Releasing STOP mode/low-voltage STOP mode
input, INTWDT2 signal), unmasked external interrupt request signal (INTP0 to INTP7 pin input), unmasked internal
interrupt request signal from the peripheral functions operable in the STOP mode and low-voltage STOP mode, or
reset signal (reset by RESET pin input, WDT2RES signal, or low-voltage detector (LVI)).
the oscillation stabilization time has been secured.
STOP mode.
Non-maskable interrupt request
signal
Maskable interrupt request signal
The STOP mode and low-voltage STOP mode are released by a non-maskable interrupt request signal (NMI pin
After the STOP mode or low-voltage STOP mode has been released, the normal operation mode is restored after
For re-setting after the low-voltage STOP mode is released, see 21.6.3 Re-setting after release of low-voltage
(1) Releasing STOP mode by non-maskable interrupt request signal or unmasked maskable interrupt
(2) Releasing STOP mode by reset
request signal
The STOP mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt
request signal, regardless of the priority of the interrupt request signal. If the STOP mode is set in an interrupt
servicing routine, however, an interrupt request signal that is issued later is serviced as follows.
(a) If an interrupt request signal with a priority lower than that of the interrupt request currently being serviced
(b) If an interrupt request signal with a priority higher than that of the interrupt request currently being serviced
The same operation as the normal reset operation is performed.
Caution The interrupt request that is disabled by setting the PSC.NMI1M, PSC.NMI0M, and PSC.INTM
Release Source
is issued, the STOP mode is released, but that interrupt request signal is not acknowledged. The interrupt
request signal itself is retained.
is issued (including a non-maskable interrupt request signal), the STOP mode is released and that
interrupt request signal is acknowledged.
Table 21-10. Operation After Releasing STOP Mode by Interrupt Request Signal
bits to 1 becomes invalid and STOP mode is not released.
Execution branches to the handler address after securing the oscillation stabilization time.
Execution branches to the handler address
or the next instruction is executed after
securing the oscillation stabilization time.
CHAPTER 21 STANDBY FUNCTION
Preliminary User’s Manual U18952EJ1V0UD
Interrupt Enabled (EI) Status
The next instruction is executed after
securing the oscillation stabilization time.
Interrupt Disabled (DI) Status
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