UPD70F3736GK-GAK-AX Renesas Electronics America, UPD70F3736GK-GAK-AX Datasheet - Page 154
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UPD70F3736GK-GAK-AX
Manufacturer Part Number
UPD70F3736GK-GAK-AX
Description
MCU 32BIT V850ES/JX3-L 80-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet
1.UPD70F3736GK-GAK-AX.pdf
(830 pages)
Specifications of UPD70F3736GK-GAK-AX
Package / Case
*
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Speed
20MHz
Number Of I /o
66
Core Processor
RISC
Program Memory Type
FLASH
Ram Size
16K x 8
Program Memory Size
256KB (256K x 8)
Data Converters
A/D 8x10b, D/A 1x8b
Oscillator Type
Internal
Peripherals
DMA, LVD, PWM, WDT
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3736GK-GAK-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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5.2
5.2.1
5.2.2
154
AD0 to AD15
A16, A17
WAIT
CLKOUT
WR0, WR1
RD
ASTB
HLDRQ
HLDAK
The pins used to connect an external device are listed in the table below.
When the internal ROM, internal RAM, or on-chip peripheral I/O are accessed, the status of each pin is as follows.
Caution When a write access is performed to the internal ROM area, address, data, and control signals
For the pin status of the V850ES/JF3-L in each operation mode, see 2.2 Pin States.
Bus Control Pins
Bus Control Pin
Table 5-2. Pin Statuses When Internal ROM, Internal RAM, or On-Chip Peripheral I/O Is Accessed
Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed
Pin status in each operation mode
are activated in the same way as access to the external memory area.
Address/data bus (AD15 to AD0)
Address bus (A17, A16)
Control signal
Bus Control Pin
PDL0 to PDL15
PDH0, PDH1
PCM0
PCM1
PCT0, PCT1
PCT4
PCT6
PCM3
PCM2
Alternate-Function Pin
CHAPTER 5 BUS CONTROL FUNCTION
Preliminary User’s Manual U18952EJ1V0UD
Table 5-1. Bus Control Pins
Hi-Z
Inactive
Low level
Output
Output
Output
Output
Output
Output
Internal ROM/RAM
Input
Input
I/O
I/O
Address/data bus
Address bus
External wait control
Internal system clock
Write strobe signal
Read strobe signal
Address strobe signal
Bus hold control
Multiplexed Bus Mode
Hi-Z
Undefined
Inactive
Peripheral I/O
Function
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