UPD70F3736GK-GAK-AX Renesas Electronics America, UPD70F3736GK-GAK-AX Datasheet - Page 180
UPD70F3736GK-GAK-AX
Manufacturer Part Number
UPD70F3736GK-GAK-AX
Description
MCU 32BIT V850ES/JX3-L 80-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet
1.UPD70F3736GK-GAK-AX.pdf
(830 pages)
Specifications of UPD70F3736GK-GAK-AX
Package / Case
*
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Speed
20MHz
Number Of I /o
66
Core Processor
RISC
Program Memory Type
FLASH
Ram Size
16K x 8
Program Memory Size
256KB (256K x 8)
Data Converters
A/D 8x10b, D/A 1x8b
Oscillator Type
Internal
Peripherals
DMA, LVD, PWM, WDT
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3736GK-GAK-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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(a) Example of setting main clock operation → subclock operation
<1> CK3 bit ← 1:
<2> Subclock operation: Read the CLS bit to check if subclock operation has started. It takes the
<3> MCK bit ← 1:
Cautions 1. When stopping the main clock, stop the PLL. Also stop the operations of the on-chip
Remark Internal system clock (f
[Description example]
<1> _SET_SUB_RUN :
<2> _CHECK_CLS :
<3> _STOP_MAIN_CLOCK :
Remark The description above is simply an example. Note that in <2> above, the CLS bit is read in a
_DMA_DISABLE:
clrl
st.b
set1
tst1
bz
st.b
set1
_DMA_ENABLE:
setl
2. If the following conditions are not satisfied, change the CK2 to CK0 bits so that the
closed loop.
peripheral functions operating with the main clock.
conditions are satisfied, then change to the subclock operation mode.
Internal system clock (f
0, DCHCn[r0]
r0, PRCMD[r0]
3, PCC[r0]
4, PCC[r0]
_CHECK_CLS
r0, PRCMD[r0]
6, PCC[r0]
0, DCHCn[r0]
CHAPTER 6 CLOCK GENERATION FUNCTION
Use of a bit manipulation instruction is recommended. Do not change the CK2
to CK0 bits.
following time after the CK3 bit is set until subclock operation is started.
Set the MCK bit to 1 only when stopping the main clock.
Preliminary User’s Manual U18952EJ1V0UD
Max.: 1/f
CLK
): Clock generated from the main clock (f
XT
CK0
(1/subclock frequency)
CLK
) > Subclock (f
-- DMA operation disabled. n = 0 to 3
-- CK3 bit ← 1
-- Wait until subclock operation starts.
-- MCK bit ← 1, main clock is stopped.
-- DMA operation enabled. n = 0 to 3
XT
: 32.768 kHz) × 4
XX
) by setting bits CK2 to
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