UPD70F3736GK-GAK-AX Renesas Electronics America, UPD70F3736GK-GAK-AX Datasheet - Page 358
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD70F3736GK-GAK-AX
Manufacturer Part Number
UPD70F3736GK-GAK-AX
Description
MCU 32BIT V850ES/JX3-L 80-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet
1.UPD70F3736GK-GAK-AX.pdf
(830 pages)
Specifications of UPD70F3736GK-GAK-AX
Package / Case
*
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Speed
20MHz
Number Of I /o
66
Core Processor
RISC
Program Memory Type
FLASH
Ram Size
16K x 8
Program Memory Size
256KB (256K x 8)
Data Converters
A/D 8x10b, D/A 1x8b
Oscillator Type
Internal
Peripherals
DMA, LVD, PWM, WDT
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3736GK-GAK-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 358 of 830
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358
(2) Operation timing in free-running timer mode
(a) Interval operation with compare register
When 16-bit timer/event counter Q is used as an interval timer with the TQ0CCRm register used as a
compare register, software processing is necessary for setting a comparison value to generate the next
interrupt request signal each time the INTTQ0CCm signal has been detected.
INTTQ0CC0 signal
INTTQ0CC1 signal
INTTQ0CC2 signal
INTTQ0CC3 signal
TQ0CCR0 register
TQ0CCR1 register
TQ0CCR2 register
TQ0CCR3 register
TOQ00 pin output
TOQ01 pin output
TOQ02 pin output
TOQ03 pin output
16-bit counter
TQ0CE bit
FFFFH
0000H
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
Interval period
Interval period
Interval period
(D
(D
(D
00
D
D
D
Preliminary User’s Manual U18952EJ1V0UD
+ 1)
10
20
00
10
20
Interval period
+ 1)
+ 1)
D
(D
00
D
30
D
30
Interval period
10
+ 1)
D
(D
20
(10000H + D
01
Interval period
− D
(D
Interval period
D
00
11
D
01
)
− D
01
D
D
Interval period
10
11
30
D
(10000H +
)
D
11
02
D
21
(10000H + D
− D
21
(10000H + D
− D
Interval period
D
01
D
Interval period
21
)
20
D
02
)
02
Interval period
Interval period
D
(D
(D
12
12
22
03
− D
D
D
− D
12
− D
31
11
31
)
D
− D
02
D
D
21
)
22
Interval period
03
03
)
(D
30
D
)
Interval period
13
22
D
(10000H + D
(D
− D
D
31
04
13
Interval period
12
− D
)
D
D
03
13
D
04
)
04
D
23
23
D
− D
32
D
D
D
23
14
22
05
)
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