UPD70F3736GK-GAK-AX Renesas Electronics America, UPD70F3736GK-GAK-AX Datasheet - Page 582
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UPD70F3736GK-GAK-AX
Manufacturer Part Number
UPD70F3736GK-GAK-AX
Description
MCU 32BIT V850ES/JX3-L 80-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet
1.UPD70F3736GK-GAK-AX.pdf
(830 pages)
Specifications of UPD70F3736GK-GAK-AX
Package / Case
*
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Speed
20MHz
Number Of I /o
66
Core Processor
RISC
Program Memory Type
FLASH
Ram Size
16K x 8
Program Memory Size
256KB (256K x 8)
Data Converters
A/D 8x10b, D/A 1x8b
Oscillator Type
Internal
Peripherals
DMA, LVD, PWM, WDT
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3736GK-GAK-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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17.8 Interrupt Request Signal (INTIICn) Generation Timing and Wait Control
corresponding wait control, as shown below (n = 0, 1).
582
The setting of the IICCn.WTIMn bit determines the timing by which the INTIICn register is generated and the
Notes 1.
Remarks 1. The numbers in the table indicate the number of the serial clock’s clock signals. Interrupt requests
(1) During address transmission/reception
(2) During data reception
(3) During data transmission
WTIMn Bit
• Slave device operation: Interrupt and wait timing are determined regardless of the WTIMn bit.
• Master device operation: Interrupt and wait timing occur at the falling edge of the ninth clock regardless of
• Master/slave device operation: Interrupt and wait timing is determined according to the WTIMn bit.
• Master/slave device operation: Interrupt and wait timing is determined according to the WTIMn bit.
0
1
2.
2. n = 0, 1
The slave device’s INTIICn signal and wait period occur at the falling edge of the ninth clock only when
there is a match with the address set to the SVAn register.
At this point, the ACK is generated regardless of the value set to the IICCn.ACKEn bit. For a slave
device that has received an extension code, the INTIICn signal occurs at the falling edge of the eighth
clock.
When the address does not match after restart, the INTIICn signal is generated at the falling edge of the
ninth clock, but no wait occurs.
If the received address does not match the contents of the SVAn register and an extension code is not
received, neither the INTIICn signal nor a wait occurs.
and wait control are both synchronized with the falling edge of these clock signals.
Address
9
9
Notes 1, 2
Notes 1, 2
During Slave Device Operation
Table 17-3. INTIICn Generation Timing and Wait Control
Data Reception
the WTIMn bit.
8
9
Note 2
Note 2
Preliminary User’s Manual U18952EJ1V0UD
CHAPTER 17 I
Data Transmission
8
9
Note 2
Note 2
2
C BUS
Address
9
9
During Master Device Operation
Data Reception
8
9
Data Transmission
8
9
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