UPD70F3736GK-GAK-AX Renesas Electronics America, UPD70F3736GK-GAK-AX Datasheet - Page 546
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD70F3736GK-GAK-AX
Manufacturer Part Number
UPD70F3736GK-GAK-AX
Description
MCU 32BIT V850ES/JX3-L 80-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet
1.UPD70F3736GK-GAK-AX.pdf
(830 pages)
Specifications of UPD70F3736GK-GAK-AX
Package / Case
*
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Speed
20MHz
Number Of I /o
66
Core Processor
RISC
Program Memory Type
FLASH
Ram Size
16K x 8
Program Memory Size
256KB (256K x 8)
Data Converters
A/D 8x10b, D/A 1x8b
Oscillator Type
Internal
Peripherals
DMA, LVD, PWM, WDT
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3736GK-GAK-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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546
After reset: 00H
(n = 0, 1)
IICFn
Note Bits 6 and 7 are read-only bits.
Cautions 1. Write the STCENn bit only when operation is stopped (IICEn bit = 0).
Condition for clearing (STCFn bit = 0)
• Cleared by IICCn.STTn bit = 1
• When the IICCn.IICEn bit = 0
• After reset
Condition for clearing (IICBSYn bit = 0)
• When stop condition is detected
• When the IICEn bit = 0
• After reset
Condition for clearing (STCENn bit = 0)
• When start condition is detected
• After reset
STCENn
Condition for clearing (IICRSVn bit = 0)
• Clearing by instruction
• After reset
IICBSYn
IICRSVn
STCFn
STCFn
<7>
0
1
0
1
0
1
0
1
2. When the STCENn bit = 1, the bus released status (IICBSYn bit = 0) is recognized
3. Write the IICRSVn bit only when operation is stopped (IICEn bit = 0).
R/W
Start condition issued
Start condition cannot be issued, STTn bit cleared
Bus released status (default communication status when STCENn bit = 1)
Bus communication status (default communication status when STCENn bit = 0)
Start conditions cannot be generated until a stop condition is detected following operation enable
(IICEn bit = 1).
Start conditions can be generated even if a stop condition is not detected following operation enable
(IICEn bit = 1).
Communication reservation enabled
Communication reservation disabled
IICBSYn
regardless of the actual bus status immediately after the I
enabled. Therefore, to issue the first start condition (STTn bit = 1), it is necessary
to confirm that the bus has been released, so as to not disturb other
communications.
<6>
Note
Address: IICF0 FFFFFD8AH, IICF1 FFFFFD9AH
5
0
Preliminary User’s Manual U18952EJ1V0UD
CHAPTER 17 I
Communication reservation function disable bit
4
0
Initial start enable trigger
3
0
I
2
2
C BUS
STTn bit clear
C0n bus status
Condition for setting (STCFn bit = 1)
• When start condition is not issued and STTn flag is
Condition for setting (IICBSYn bit = 1)
• When start condition is detected
• By setting the IICEn bit when the STCENn bit = 0
Condition for setting (STCENn bit = 1)
• Setting by instruction
Condition for setting (IICRSVn bit = 1)
• Setting by instruction
cleared to 0 during communication reservation is
disabled (IICRSVn bit = 1).
2
0
STCENn
<1>
IICRSVn
2
Cn bus operation is
<0>
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