UPD70F3736GK-GAK-AX Renesas Electronics America, UPD70F3736GK-GAK-AX Datasheet - Page 470
UPD70F3736GK-GAK-AX
Manufacturer Part Number
UPD70F3736GK-GAK-AX
Description
MCU 32BIT V850ES/JX3-L 80-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet
1.UPD70F3736GK-GAK-AX.pdf
(830 pages)
Specifications of UPD70F3736GK-GAK-AX
Package / Case
*
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Speed
20MHz
Number Of I /o
66
Core Processor
RISC
Program Memory Type
FLASH
Ram Size
16K x 8
Program Memory Size
256KB (256K x 8)
Data Converters
A/D 8x10b, D/A 1x8b
Oscillator Type
Internal
Peripherals
DMA, LVD, PWM, WDT
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
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Price
Company:
Part Number:
UPD70F3736GK-GAK-AX
Manufacturer:
Renesas Electronics America
Quantity:
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15.6.9 Parity types and operations
transmission side and the reception side.
parity, errors cannot be detected.
470
Caution When using the LIN function, fix the UAnPS1 and UAnPS0 bits of the UAnCTL0 register to 00.
The parity bit is used to detect bit errors in the communication data. Normally the same parity is used on the
In the case of even parity and odd parity, it is possible to detect odd-count bit errors. In the case of 0 parity and no
(a) Even parity
(b) Odd parity
(c) 0 parity
(d) No parity
(i) During transmission
(ii) During reception
(i) During transmission
(ii) During reception
During transmission, the parity bit is always made 0, regardless of the transmit data.
During reception, parity bit check is not performed. Therefore, no parity error occurs, regardless of whether the
parity bit is 0 or 1.
No parity bit is added to the transmit data.
Reception is performed assuming that there is no parity bit. No parity error occurs since there is no parity bit.
The number of bits whose value is “1” among the transmit data, including the parity bit, is controlled so as
to be an even number. The parity bit values are as follows.
• Odd number of bits whose value is “1” among transmit data: 1
• Even number of bits whose value is “1” among transmit data: 0
The number of bits whose value is “1” among the reception data, including the parity bit, is counted, and if
it is an odd number, a parity error is output.
Opposite to even parity, the number of bits whose value is “1” among the transmit data, including the parity
bit, is controlled so that it is an odd number. The parity bit values are as follows.
• Odd number of bits whose value is “1” among transmit data: 0
• Even number of bits whose value is “1” among transmit data: 1
The number of bits whose value is “1” among the receive data, including the parity bit, is counted, and if it
is an even number, a parity error is output.
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
Preliminary User’s Manual U18952EJ1V0UD
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