UPD70F3736GK-GAK-AX Renesas Electronics America, UPD70F3736GK-GAK-AX Datasheet - Page 448
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UPD70F3736GK-GAK-AX
Manufacturer Part Number
UPD70F3736GK-GAK-AX
Description
MCU 32BIT V850ES/JX3-L 80-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet
1.UPD70F3736GK-GAK-AX.pdf
(830 pages)
Specifications of UPD70F3736GK-GAK-AX
Package / Case
*
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Speed
20MHz
Number Of I /o
66
Core Processor
RISC
Program Memory Type
FLASH
Ram Size
16K x 8
Program Memory Size
256KB (256K x 8)
Data Converters
A/D 8x10b, D/A 1x8b
Oscillator Type
Internal
Peripherals
DMA, LVD, PWM, WDT
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3736GK-GAK-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 448 of 830
- Download datasheet (7Mb)
15.2 Features
448
Transfer rate: 300 bps to 625 kbps (using internal system clock of 20 MHz and dedicated baud rate generator)
Full-duplex communication: Internal UARTAn receive data register (UAnRX)
2-pin configuration:
Reception error output function
• Parity error
• Framing error
• Overrun error
Interrupt sources: 2
• Reception complete interrupt (INTUAnR):
• Transmission enable interrupt (INTUAnT):
Character length: 7, 8 bits
Parity function: Odd, even, 0, none
Transmission stop bit: 1, 2 bits
On-chip dedicated baud rate generator
MSB-/LSB-first transfer selectable
Transmit/receive data inverted input/output possible
SBF (Sync Break Field) transmission/reception in the LIN (Local Interconnect Network) communication format
• 13 to 20 bits selectable for the SBF transmission
• Recognition of 11 bits or more possible for SBF reception
• SBF reception flag provided
Remark
n = 0 to 2
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
Internal UARTAn transmit data register (UAnTX)
TXDAn: Transmit data output pin
RXDAn: Receive data input pin
Preliminary User’s Manual U18952EJ1V0UD
This interrupt occurs upon transfer of receive data from the
receive shift register to receive data register after serial
transfer completion, in the reception enabled status.
This interrupt occurs upon transfer of transmit data from the
transmit data register to the transmit shift register in the
transmission enabled status.
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