AT90LS2333-4AI Atmel, AT90LS2333-4AI Datasheet - Page 24

• Manufacturer Part Number: AT90LS2333-4AI
• Description: IC MCU 2K 4MHZ A/D LV IT 32TQFP
• Manufacturer: Atmel
• Series: AVR® 90LSr

Specifications of AT90LS2333-4AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFP, 32-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

General Interrupt Flag Register - GIFR
•
When an event on the INT1 pin triggers an interrupt request, INTF1 becomes set (one). If the I-bit in SREG and the INT1 bit
in GIMSK are set (one), the MCU will jump to the interrupt vector at address $002. The flag is cleared when the interrupt
routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
•
When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit
in GIMSK are set (one), the MCU will jump to the interrupt vector at address $001. The flag is cleared when the interrupt
routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
•
These bits are reserved bits in the AT90S2333/4433 and always read as zero.
Timer/Counter Interrupt Mask Register - TIMSK
•
When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is
enabled. The corresponding interrupt (at vector $005) is executed if an overflow in Timer/Counter1 occurs, i.e., when the
TOV1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
•
When the OCIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Compare Match inter-
rupt is enabled. The corresponding interrupt (at vector $004) is executed if a Compare match in Timer/Counter1 occurs,
i.e., when the OCF1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
•
These bits are reserved bits in the AT90S2333/4433 and always read as 0.
•
When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event
Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin 14,
PB0 (ICP), i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
•
This bit is a reserved bit in the AT90S2333/4433 and always reads as 0.
•
When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is
enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter0 occurs, i.e., when the
TOV0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
•
This bit is a reserved bit in the AT90S2333/4433 and always reads as zero.
24
Bit
$3A ($5A)
Read/Write
Initial value
Bit
$39 ($59)
Read/Write
Initial value
Bit 7 - INTF1: External Interrupt Flag1
Bit 6 - INTF0: External Interrupt Flag0
Bits 5..0 - Res: Reserved bits
Bit 7 - TOIE1: Timer/Counter1 Overflow Interrupt Enable
Bit 6 - OCIE1: Timer/Counter1 Output Compare Match Interrupt Enable
Bit 5, 4 - Res: Reserved Bits
Bit 3 - TICIE1: Timer/Counter1 Input Capture Interrupt Enable
Bit 2 - Res: Reserved Bit
Bit 1 - TOIE0: Timer/Counter0 Overflow Interrupt Enable
Bit 0 - Res: Reserved bit
AT90S/LS2333 and AT90S/LS4433
INTF1
R/W
TOIE1
R/W
7
0
7
0
INTF0
R/W
6
0
OCIE1
R/W
6
0
R
5
0
-
R
5
0
-
R
4
0
-
R
4
0
-
R
3
0
-
TICIE1
R/W
3
0
R
2
0
-
R
2
0
-
R
1
0
-
TOIE0
R/W
1
0
R
0
0
-
R
0
0
-
GIFR
TIMSK