AT90LS2333-4AI Atmel, AT90LS2333-4AI Datasheet - Page 48

• Manufacturer Part Number: AT90LS2333-4AI
• Description: IC MCU 2K 4MHZ A/D LV IT 32TQFP
• Manufacturer: Atmel
• Series: AVR® 90LSr

Specifications of AT90LS2333-4AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFP, 32-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

•
This bit is set if an Overrun condition is detected, i.e. when a character already present in the UDR register is not read
before the next character has been shifted into the Receiver Shift register. The OR bit is buffered, which means that it will
be set once the valid data still in UDRE is read.
The OR bit is cleared (zero) when data is received and transferred to UDR.
•
These bits are reserved bits in the AT90S2333/4433 and will always read as zero.
•
This bit is used to enter Multi-Processor Communication Mode. The bit is set when the slave MCU waits for an address
byte to be received. When the MCU has been addressed, the MCU switches off the MPCM bit, and starts data reception.
For a detailed description, see “Multi-Processor Communication Mode”.
UART Control and Status Registers - UCSRB
•
When this bit is set (one), a setting of the RXC bit in USR will cause the Receive Complete interrupt routine to be executed
provided that global interrupts are enabled.
•
When this bit is set (one), a setting of the TXC bit in USR will cause the Transmit Complete interrupt routine to be executed
provided that global interrupts are enabled.
•
When this bit is set (one), a setting of the UDRE bit in USR will cause the UART Data Register Empty interrupt routine to be
executed provided that global interrupts are enabled.
•
This bit enables the UART receiver when set (one). When the receiver is disabled, the TXC, OR and FE status flags cannot
become set. If these flags are set, turning off RXEN does not cause them to be cleared.
•
This bit enables the UART transmitter when set (one). When disabling the transmitter while transmitting a character, the
transmitter is not disabled before the character in the shift register plus any following character in UDR has been com-
pletely transmitted.
•
When this bit is set (one) transmitted and received characters are 9 bit long plus start and stop bits. The 9th bit is read and
written by using the RXB8 and TXB8 bits in UCR, respectively. The 9th data bit can be used as an extra stop bit or a parity
bit.
•
When CHR9 is set (one), RXB8 is the 9th data bit of the received character.
•
When CHR9 is set (one), TXB8 is the 9th data bit in the character to be transmitted.
Baud Rate Generator
The baud rate generator is a frequency divider which generates baud-rates according to the following equation:
• BAUD = Baud-Rate
• f
• UBR = Contents of the UBRRH and UBRR registers, (0-4095)
48
Bit
$0A ($2A)
Read/Write
Initial value
Bit 3 - OR: OverRun
Bits 2..1 - Res: Reserved bits
Bit 0 - MPCM: Multi-Processor Communication Mode
Bit 7 - RXCIE: RX Complete Interrupt Enable
Bit 6 - TXCIE: TX Complete Interrupt Enable
Bit 5 - UDRIE: UART Data Register Empty Interrupt Enable
Bit 4 - RXEN: Receiver Enable
Bit 3 - TXEN: Transmitter Enable
Bit 2 - CHR9: 9 Bit Characters
Bit 1 - RXB8: Receive Data Bit 8
Bit 0 - TXB8: Transmit Data Bit 8
CK
= Crystal Clock frequency
AT90S/LS2333 and AT90S/LS4433
RXCIE
R/W
7
0
TXCIE
R/W
6
0
UDRIE
R/W
5
0
RXEN
R/W
4
0
BAUD
TXEN
R/W
=
3
0
---------------------------------
16(UBR
f
CK
CHR9
R/W
2
0
+
1
RXB8
R
1
1
TXB8
W
0
0
UCSRB