AT90LS2333-4AI Atmel, AT90LS2333-4AI Datasheet - Page 41

• Manufacturer Part Number: AT90LS2333-4AI
• Description: IC MCU 2K 4MHZ A/D LV IT 32TQFP
• Manufacturer: Atmel
• Series: AVR® 90LSr

Specifications of AT90LS2333-4AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFP, 32-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Figure 37. SPI Master-Slave Interconnection
The system is single buffered in the transmit direction and double buffered in the receive direction. This means that bytes to
be transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed. When receiving data,
however, a received byte must be read from the SPI Data Register before the next byte has been completely shifted in.
Otherwise, the first byte is lost.
When the SPI is enabled, the data direction of the MOSI, MISO, SCK and SS pins is overridden according to the following
table:
Table 17. SPI Pin Direction Overrides
Note:
SS Pin Functionality
When the SPI is configured as a master (MSTR in SPCR is set), the user can determine the direction of the SS pin. If SS is
configured as an output, the pin is a general output pin which does not affect the SPI system. If SS is configured as an
input, it must be hold high to ensure Master SPI operation. If the SS pin is driven low by peripheral circuitry when the SPI is
configured as master with the SS pin defined as an input, the SPI system interprets this as another master selecting the
SPI as a slave and starting to send data to it. To avoid bus contention, the SPI system takes the following actions:
1. The MSTR bit in SPCR is cleared and the SPI system becomes a slave. As a result of the SPI becoming a slave, the
2. The SPIF flag in SPSR is set, and if the SPI interrupt is enabled and the I-bit in SREG is set, the interrupt routine will
Thus, when interrupt-driven SPI transmittal is used in master mode, and there exists a possibility that SS is driven low, the
interrupt should always check that the MSTR bit is still set. Once the MSTR bit has been cleared by a slave select, it must
be set by the user to re-enale the SPI master mode.
When the SPI is configured as a slave, the SS pin is always input. When SS is held low, the SPI is activated and MISO
becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, externally all pins are
inputs, and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once
the SS pin is brought high. If the SS pin is brought high during a transmission, the SPI will stop sending and receiving
immediately and both data received and data sent must be considered as lost.
MOSI and SCK pins become inputs.
be executed.
MOSI
MISO
SCK
See “Alternate Functions Of Port B” on page 60 f
SPI pins.
Pin
SS
Direction Overrides, Master SPI Mode
User Defined
Input
User Defined
User Defined
AT90S/LS2333 and AT90S/LS4433
or a detailed description og how to define the direction of the user defined
Input
Direction Overrides, Slave SPI Modes
User Defined
Input
Input
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