AT90LS2333-4AI Atmel, AT90LS2333-4AI Datasheet - Page 38

• Manufacturer Part Number: AT90LS2333-4AI
• Description: IC MCU 2K 4MHZ A/D LV IT 32TQFP
• Manufacturer: Atmel
• Series: AVR® 90LSr

Specifications of AT90LS2333-4AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFP, 32-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

EEPROM Read/Write Access
The EEPROM access registers are accessible in the I/O space.
The write access time is in the range of 2.5 - 4ms, depending on the V
ware detect when the next byte can be written. A special EEPROM Ready interrupt can be set to trigger when the
EEPROM is ready to accept new data.
An ongoing EEPROM write operation will complete even if a reset condition occurs.
In order to prevent unintentional EEPROM writes, a two state write procedure must be followed. Refer to the description of
the EEPROM Control Register for details on this.
When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed.
EEPROM Address Register - EEAR
The EEPROM Address Register - EEAR specifies the EEPROM address in the 128/256 bytes EEPROM space. The
EEPROM data bytes are addressed linearly between 0 and 127/255. The initial value of EEAR is undefined. A proper value
must be written before the EEPROM may be accessed.
EEPROM Data Register - EEDR
•
For the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given
by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the
address given by EEAR.
EEPROM Control Register - EECR
•
These bits are reserved bits in the AT90S2333/4433 and will always read as zero.
•
When the I bit in SREG and EERIE are set (one), the EEPROM Ready Interrupt is enabled. When cleared (zero), the inter-
rupt is disabled. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared (zero).
•
The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set(one)
setting EEWE will write data to the EEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect.
When EEMWE has been set (one) by software, hardware clears the bit to zero after four clock cycles. See the description
of the EEWE bit for a EEPROM write procedure.
38
Bit
$1E ($3E)
Read/Write
Initial value
Bit
$1D ($3D)
Read/Write
Initial value
Bit
$1C ($3C)
Read/Write
Initial value
Bits 7..0 - EEDR7.0: EEPROM Data
Bit 7..4 - Res: Reserved bits
Bit 3 - EERIE: EEPROM Ready Interrupt Enable
Bit 2 - EEMWE: EEPROM Master Write Enable
AT90S/LS2333 and AT90S/LS4433
EEAR7
MSB
R/W
R/W
R
7
X
7
0
7
0
-
EEAR6
R/W
R/W
X
R
6
6
0
6
0
-
EEAR5
R/W
R/W
X
R
5
5
0
5
0
-
EEAR4
R/W
R/W
R
4
X
4
0
4
0
-
EEAR3
EERIE
R/W
R/W
R/W
3
X
3
0
3
0
EEMWE
EEAR2
R/W
R/W
R/W
X
2
2
0
2
0
CC
voltages. A self-timing function lets the user soft-
EEAR1
EEWE
R/W
R/W
R/W
X
1
1
0
1
0
EEAR0
EERE
R/W
LSB
R/W
R/W
X
0
0
0
0
0
EECR
EEAR
EEDR