PIC18F4431-E/ML Microchip Technology, PIC18F4431-E/ML Datasheet - Page 125

• Manufacturer Part Number: PIC18F4431-E/ML
• Description: IC MCU FLASH 8KX16 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4431-E/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE 11-9:
TABLE 11-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
 2010 Microchip Technology Inc.
PORTE
LATE
TRISE
ANSEL0
ANSEL1
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
Note 1:
RE0/AN6
RE1/AN7
RE2/AN8
MCLR/V
Legend:
Note 1:
Name
2:
2:
Pin
PP
/RE3
Implemented only when Master Clear functionality is disabled (CONFIG3H<7> = 0). It is available for
PIC18F4331/4431 devices only.
ANS5 through ANS8 are available only on PIC18F4331/4431 devices.
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
All PORTE pins are only implemented on 40/44-pin devices.
RE3 does not have a corresponding TRIS bit to control data direction.
ANS7
(1)
Bit 7
—
—
—
—
PORTE I/O SUMMARY
Function
(2)
MCLR
RE0
AN6
RE1
AN7
RE2
AN8
RE3
V
PP
ANS6
Bit 6
—
—
—
—
Setting
(2)
TRIS
—
—
—
0
1
1
0
1
1
0
1
1
(2)
ANS5
Bit 5
—
—
—
—
I/O
O
O
O
(2)
I
I
I
I
I
I
I
I
I
PIC18F2331/2431/4331/4431
ANS4
Type
ANA
ANA
ANA
ANA
Bit 4
DIG
DIG
DIG
I/O
ST
ST
ST
ST
ST
—
—
—
—
LATE<0> data output; not affected by analog input.
PORTE<0> data input; disabled when analog input is enabled.
A/D Input Channel 6. Default input configuration on POR.
LATE<1> data output; not affected by analog input.
PORTE<1> data input; disabled when analog input is enabled.
A/D Input Channel 7. Default input configuration on POR.
LATE<2> data output; not affected by analog input.
PORTE<2> data input; disabled when analog input is enabled.
A/D Input Channel 8. Default input configuration on POR.
External Master Clear input; enabled when MCLRE Configuration bit
is set.
High-Voltage Detection; used for ICSP™ mode entry detection. Always
available, regardless of pin mode.
PORTE<3> data input; enabled when MCLRE Configuration bit is
clear.
RE3
ANS3
Bit 3
—
—
—
(1)
LATE Data Output Register
PORTE Data Direction Register
ANS2
Bit 2
RE2
—
Description
ANS1
Bit 1
RE1
—
ANS8
ANS0
Bit 0
RE0
(2)
DS39616D-page 125
Reset Values
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