PIC18F4431-E/ML Microchip Technology, PIC18F4431-E/ML Datasheet - Page 167

• Manufacturer Part Number: PIC18F4431-E/ML
• Description: IC MCU FLASH 8KX16 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4431-E/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.2.6
The velocity pulse generator, in conjunction with the
IC1 and the synchronous TMR5 (in synchronous
operation), provides a method for high accuracy speed
measurements at both low and high mechanical motor
speeds. The Velocity mode is enabled when the VELM
bit is cleared (= 0) and QEI is set to one of its operating
modes (see
To optimize register space, the Input Capture
Channel 1 (IC1) is used to capture TMR5 counter
values. Input Capture Buffer register, CAP1BUF, is
redefined in Velocity Measurement mode, VELM = 0,
as the Velocity Register Buffer (VELRH, VELRL).
TABLE 17-6:
FIGURE 17-12:
 2010 Microchip Technology Inc.
QEIM<2:0>
CAP1/INDX
CAP2/QEA
001
010
101
110
CAP3/QEB
VELOCITY MEASUREMENT
Table
x2 Velocity Event mode. The velocity
pulse is generated on every QEA edge.
x4 Velocity Event mode. The velocity
pulse is generated on every QEA and
QEB active edge.
VELOCITY PULSES
17-6).
VELOCITY MEASUREMENT BLOCK DIAGRAM
Velocity Event Mode
QEB
QEA
INDX
Control
Logic
Velocity Event
QEI
Direction
Clock
PIC18F2331/2431/4331/4431
Postscaler
Reset
Logic
Position
Counter
TMR5 Reset
17.2.6.1
The event pulses are reduced by a fixed ratio by the
velocity pulse divider. The divider is useful for
high-speed measurements where the velocity events
happen frequently. By producing a single output pulse
for a given number of input event pulses, the counter
can track larger pulse counts (i.e., distance travelled)
for a given time interval. Time is measured by utilizing
the TMR5 time base.
Each velocity pulse serves as a capture pulse. With the
TMR5 in Synchronous Timer mode, the value of TMR5
is captured on every output pulse of the postscaler. The
counter is subsequently reset to ‘0’. TMR5 is reset
upon a capture event.
Figure 17-13
diagram.
Velocity Capture
Velocity Event Timing
shows the velocity measurement timing
(VELR Register)
TMR5
IC1
16
Clock
DS39616D-page 167
Velocity Mode
T
CY