PIC18F4431-E/ML Microchip Technology, PIC18F4431-E/ML Datasheet - Page 206

• Manufacturer Part Number: PIC18F4431-E/ML
• Description: IC MCU FLASH 8KX16 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4431-E/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F2331/2431/4331/4431
REGISTER 19-1:
DS39616D-page 206
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W-0
SMP
SMP: Sample bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode.
CKE: SPI Clock Edge Select bit
SPI mode, CKP = 0:
1 = Data transmitted on rising edge of SCK
0 = Data transmitted on falling edge of SCK
SPI mode, CKP = 1:
1 = Data transmitted on falling edge of SCK
0 = Data transmitted on rising edge of SCK
I
This bit must be maintained clear.
D/A: Data/Address bit (I
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
P: Stop bit (I
This bit is cleared when the SSP module is disabled or when the Start bit is detected last; SSPEN is
cleared.
1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset)
0 = Stop bit was not detected last
S: Start bit (I
This bit is cleared when the SSP module is disabled or when the Stop bit is detected last; SSPEN is
cleared.
1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)
0 = Start bit was not detected last
R/W: Read/Write Information bit (I
This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next Start bit, Stop bit or ACK bit.
1 = Read
0 = Write
UA: Update Address bit (10-Bit I
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
BF: Buffer Full Status bit
Receive (SPI and I
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I
1 = Transmit in progress, SSPBUF is full
0 = Transmit complete, SSPBUF is empty
2
C™ mode:
R/W-0
CKE
SSPSTAT: SYNCHRONOUS SERIAL PORT STATUS REGISTER
2
C mode only):
2
2
C mode only)
C mode only)
W = Writable bit
‘1’ = Bit is set
2
R-0
D/A
C modes):
2
C mode only)
2
(Figure
C mode only)
2
R-0
C mode only)
P
19-2,
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
Figure 19-3
R-0
S
and
Figure
R/W
R-0
19-4)
 2010 Microchip Technology Inc.
x = Bit is unknown
R-0
UA
R-0
BF
bit 0