PIC18F4431-E/ML Microchip Technology, PIC18F4431-E/ML Datasheet - Page 198

IC MCU FLASH 8KX16 44QFN

PIC18F4431-E/ML

Manufacturer Part Number
PIC18F4431-E/ML
Description
IC MCU FLASH 8KX16 44QFN
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F4431-E/ML

Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
PIC18F2331/2431/4331/4431
18.11 PWM Output and Polarity Control
There are three device Configuration bits associated
with the PWM module that provide PWM output pin
control defined in the CONFIG3L Configuration
register. They are:
• HPOL
• LPOL
• PWMPIN
These three Configuration bits work in conjunction with
the three PWM Enable bits (PWMEN<2:0>) in the
PWMCON0 register. The Configuration bits and PWM
enable bits ensure that the PWM pins are in the correct
states after a device Reset occurs.
18.11.1
The PWMEN<2:0> control bits enable each PWM
output pin as required in the application.
All PWM I/O pins are general purpose I/O. When a pair
of pins are enabled for PWM output, the PORT and
TRIS registers controlling the pins are disabled. Refer
to
FIGURE 18-23:
DS39616D-page 198
Figure 18-23
OUTPUT PIN CONTROL
Note:
for details.
PWM Signal from Module
PWM Pin Enable
Data Bus
WR PORT
WR TRIS
RD TRIS
RD PORT
PWM I/O PIN BLOCK DIAGRAM
I/O pin has protection diodes to V
Data Latch
TRIS Latch
D
D
CK
CK
Q
Q
Q
Q
DD
and V
1
0
SS
. PWM polarity selection logic not shown for clarity.
18.11.2
The polarity of the PWM I/O pins is set during device
programming via the HPOL and LPOL Configuration
bits in the CONFIG3L Configuration register. The
HPOL Configuration bit sets the output polarity for the
high side PWM outputs: PWM1, PWM3, PWM5 and
PWM7. The polarity is active-low when HPOL is
cleared (= 0), and active-high when it is set (= 1).
The LPOL Configuration bit sets the output polarity for
the low side PWM outputs: PWM0, PWM2, PWM4 and
PWM6. As with HPOL, they are active-low when LPOL
is cleared and active-high when it is set.
All output signals generated by the PWM module are
referenced to the polarity control bits, including those
generated by Fault inputs or manual override (see
Section 18.10 “PWM Output
The default polarity Configuration bits have the PWM
I/O pins in active-high output polarity.
Q
EN
D
OUTPUT POLARITY CONTROL
V
V
P
N
DD
SS
 2010 Microchip Technology Inc.
Override”).
TTL or
Schmitt
Trigger
I/O Pin

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