PIC18F4431-E/ML Microchip Technology, PIC18F4431-E/ML Datasheet - Page 95

• Manufacturer Part Number: PIC18F4431-E/ML
• Description: IC MCU FLASH 8KX16 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4431-E/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.0
9.1
All PIC18 devices include an 8 x 8 hardware multiplier
as part of the ALU. The multiplier performs an unsigned
operation and yields a 16-bit result that is stored in the
product register pair, PRODH:PRODL. The multiplier’s
operation does not affect any flags in the STATUS
register.
Making multiplication a hardware operation allows it to be
completed in a single instruction cycle. This has the
advantages of higher computational throughput and
reduced code size for multiplication algorithms, and
allows the PIC18 devices to be used in many applications
previously reserved for digital signal processors.
A comparison of various hardware and software multi-
ply operations, along with the savings in memory and
execution time, is shown in
TABLE 9-1:
 2010 Microchip Technology Inc.
16 x 16 Unsigned
8 x 8 Unsigned
16 x 16 Signed
8 x 8 Signed
Routine
8 x 8 HARDWARE MULTIPLIER
Introduction
PERFORMANCE COMPARISON
Without Hardware Multiply
Without Hardware Multiply
Without Hardware Multiply
Without Hardware Multiply
Hardware Multiply
Hardware Multiply
Hardware Multiply
Hardware Multiply
Multiply Method
Table
9-1.
PIC18F2331/2431/4331/4431
Program
Memory
(Words)
13
33
21
24
52
36
1
6
9.2
Example 9-1
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
Example 9-2
multiply. To account for the sign bits of the arguments,
each argument’s Most Significant bit (MSb) is tested
and the appropriate subtractions are done.
EXAMPLE 9-1:
EXAMPLE 9-2:
MOVF
MULWF
MOVF
MULWF
BTFSC
SUBWF
MOVF
BTFSC
SUBWF
Cycles
(Max)
242
254
69
91
24
36
1
6
Operation
ARG1, W
ARG2
ARG1, W
ARG2
ARG2, SB
PRODH, F
ARG2, W
ARG1, SB
PRODH, F
shows the sequence to do an 8 x 8 signed
shows the sequence to do an 8 x 8
@ 40 MHz
24.2 s
25.4 s
100 ns
600 ns
6.9 s
9.1 s
2.4 s
3.6 s
8 x 8 UNSIGNED MULTIPLY
ROUTINE
8 x 8 SIGNED MULTIPLY
ROUTINE
;
; ARG1 * ARG2 ->
; PRODH:PRODL
; ARG1 * ARG2 ->
; PRODH:PRODL
; Test Sign Bit
; PRODH = PRODH
;
; Test Sign Bit
; PRODH = PRODH
;
@ 10 MHz
102.6 s
27.6 s
36.4 s
96.8 s
14.4 s
Time
400 ns
2.4 s
9.6 s
DS39616D-page 95
- ARG1
- ARG2
@ 4 MHz
242 s
254 s
69 s
91 s
24 s
36 s
1 s
6 s