PIC18F4431-E/ML Microchip Technology, PIC18F4431-E/ML Datasheet - Page 149

• Manufacturer Part Number: PIC18F4431-E/ML
• Description: IC MCU FLASH 8KX16 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4431-E/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.5
In Pulse-Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTC data latch,
the TRISC<2> bit must be cleared to make the CCP1
pin an output.
Figure 16-3
CCP1 module in PWM mode.
For a step-by-step procedure on how to set up the
CCP1 module for PWM operation, see
“Setup for PWM
FIGURE 16-3:
A PWM output
(period) and a time that the output is high (duty
cycle). The frequency of the PWM is the inverse of
the period (1/period).
FIGURE 16-4:
 2010 Microchip Technology Inc.
Note:
Note 1: 8-bit timer is concatenated with 2-bit internal
CCPR1H (Slave)
Duty Cycle Registers
Comparator
CCPR1L
TMR2 = PR2
TMR2
PR2
Comparator
PWM Mode
Duty Cycle
Q clock or 2 bits of the prescaler to create
10-bit time base.
Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
shows a simplified block diagram of the
Period
(Note 1)
Operation”.
(Figure
TMR2 = Duty Cycle
Clear Timer,
CCP1 pin and
latch D.C.
SIMPLIFIED PWM BLOCK
DIAGRAM
PWM OUTPUT
TMR2 = PR2
16-4) has a time base
CCP1CON<5:4>
R
S
Q
TRISC<2>
Section 16.5.3
RC2/CCP1
PIC18F2331/2431/4331/4431
16.5.1
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following equation:
EQUATION 16-1:
PWM frequency is defined as 1/[PWM period]. When
TMR2 is equal to PR2, the following three events occur
on the next increment cycle:
• TMR2 is cleared
• The CCP1 pin is set (if PWM duty cycle = 0%, the
• The PWM duty cycle is copied from CCPR1L into
16.5.2
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The PWM duty cycle is
calculated by the following equation:
EQUATION 16-2:
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not copied into
CCPR1H until a match between PR2 and TMR2 occurs
(i.e., the period is complete). In PWM mode, CCPR1H
is a read-only register.
CCP1 pin will not be set)
CCPR1H
Note:
PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) •
PWM Period = [(PR2) + 1] • 4 • T
The Timer2 postscaler (see
“Timer2
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
PWM PERIOD
PWM DUTY CYCLE
Module”) is not used in the
T
(TMR2 Prescale Value)
OSC
• (TMR2 Prescale Value)
DS39616D-page 149
OSC
Section 14.0
•