PIC18F4431-E/ML Microchip Technology, PIC18F4431-E/ML Datasheet - Page 145

• Manufacturer Part Number: PIC18F4431-E/ML
• Description: IC MCU FLASH 8KX16 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4431-E/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.0
The CCP (Capture/Compare/PWM) module contains a
16-bit register that can operate as a 16-bit Capture reg-
ister, a 16-bit Compare register or a PWM Master/Slave
Duty Cycle register.
resources required for each of the CCP module modes.
The operation of CCP1 is identical to that of CCP2, with
the exception of the Special Event Trigger. Therefore,
operation of a CCP module is described with respect to
CCP1, except where noted.
16.1
Capture/Compare/PWM
comprised of two 8-bit registers: CCPR1L (low byte)
and CCPR1H (high byte). The CCP1CON register
controls the operation of CCP1. All are readable and
writable.
REGISTER 16-1:
 2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-6
bit 5-4
bit 3-0
U-0
—
CAPTURE/COMPARE/PWM
(CCP) MODULES
CCP1 Module
Unimplemented: Read as ‘0’
DCxB<1:0>: PWM Duty Cycle bit 1 and bit 0
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSBs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The upper eight bits
(DCxB<9:2>) of the duty cycle are found in CCPRxL.
CCPxM<3:0>: CCPx Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCPx module)
0001 = Reserved
0010 = Compare mode; toggle output on match (CCPxIF bit is set)
0011 = Reserved
0100 = Capture mode; every falling edge
0101 = Capture mode; every rising edge
0110 = Capture mode; every 4th rising edge
0111 = Capture mode; every 16th rising edge
1000 = Compare mode; initialize CCPx pin low; on compare match, force CCPx pin high (CCPxIF bit is set)
1001 = Compare mode; initialize CCPx pin high; on compare match, force CCPx pin low (CCPxIF bit is set)
1010 = Compare mode; generate software interrupt on compare match (CCPxIF bit is set, CCPx pin is
1011 = Compare mode; Special Event Trigger (CCPxIF bit is set)
11xx = PWM mode
U-0
—
unaffected)
CCPxCON: CCPx CONTROL REGISTER
Table 16-1
Register
W = Writable bit
‘1’ = Bit is set
DCxB1
R/W-0
shows the timer
1
(CCPR1)
PIC18F2331/2431/4331/4431
DCxB0
R/W-0
is
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
CCPxM3
R/W-0
TABLE 16-1:
16.2
Capture/Compare/PWM Register 2 (CCPR2) is com-
prised of two 8-bit registers: CCPR2L (low byte) and
CCPR2H (high byte). The CCP2CON register controls
the operation of CCP2. All are readable and writable.
CCP Mode
Compare
Capture
CCP2 Module
PWM
CCPxM2
R/W-0
CCP MODE – TIMER
RESOURCES
x = Bit is unknown
CCPxM1
R/W-0
Timer Resources
DS39616D-page 145
Timer1
Timer1
Timer2
CCPxM0
R/W-0
bit 0