ATTINY167-15XD Atmel, ATTINY167-15XD Datasheet - Page 170

• Manufacturer Part Number: ATTINY167-15XD
• Description: MCU AVR 16K FLASH 15MHZ 20-TSSOP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY167-15XD

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 20-TSSOP
• Processor Series: ATTINY1x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.5
15.5.1
15.5.2
15.5.3
170
LIN / UART Description
ATtiny87/ATtiny167
Reset
Clock
LIN Protocol Selection
The AVR core reset logic signal also resets the LIN/UART controller. Another form of reset
exists, a software reset controlled by LSWRES bit in LINCR register. This self-reset bit per-
forms a partial reset as shown in
Table 15-2.
The I/O clock signal (clk
LIN13 bit in LINCR register is used to select the LIN protocol:
The controller checks the LIN13 bit in computing the checksum (enhanced checksum in
LIN2.1 / classic checksum in LIN 1.3).
This bit is irrelevant for UART commands.
• LIN13 = 0 (default): LIN 2.1 protocol,
• LIN13 = 1: LIN 1.3 protocol.
LIN Status & Interrupt Reg.
LIN Enable Interrupt Reg.
LIN Baud Rate Reg. High
LIN Data Buffer Selection
LIN Baud Rate Reg. Low
LIN Data Length Reg.
LIN Bit Timing Reg.
LIN Identifier Reg.
LIN Control Reg.
LIN Error Reg.
Register
LIN Data
Reset of LIN/UART Registers
i/o
) also clocks the LIN/UART controller. It is its unique clock.
LINBRRH
LINBRRL
LINENIR
LINERR
LINBTR
LINDLR
LINSEL
LINIDR
LINDAT
LINSIR
Table
LINCR
Name
15-2.
Reset Value
0000 0000
0000 0000
0000 0000
0000 0000
0010 0000
0000 0000
0000 0000
0000 0000
1000 0000
0000 0000
0000 0000
b
b
b
b
b
b
b
b
b
b
b
LSWRES Value
0000 0000
0000 0000
0000 0000
0010 0000
uuuu uuuu
0000 0000
1000 0000
0000 0000
xxxx 0000
xxxx uuuu
xxxx 0000
b
b
b
b
b
b
b
b
b
b
b
7728G–AVR–06/10
u=unchanged
x=unknown
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