ATTINY167-15XD Atmel, ATTINY167-15XD Datasheet - Page 85

• Manufacturer Part Number: ATTINY167-15XD
• Description: MCU AVR 16K FLASH 15MHZ 20-TSSOP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY167-15XD

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 20-TSSOP
• Processor Series: ATTINY1x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7728G–AVR–06/10
Table 9-8.
Signal
DIEOE
DIEOV
DDOE
PUOE
PUOV
DDOV
PVOE
Name
PVOV
PTOE
AIO
DI
OC1B_ENABLE
PB3/PCINT11/
PCMSK11
PCINT11
PCIE1 &
OC1BV
OC1BV
OC1B
Overriding Signals for Alternate Functions in PB3..PB0
&
0
0
0
0
0
1
0
USI_PTOE & USIPOS
(USISIE & USIPOS) |
(USISIE & USIPOS) |
PCINT10 -/- USCK -/-
(PCIE1 & PCMSK10)
(PCIE1 & PCMSK10)
OC1AV/USCK/SCL
(OC1A_ENABLE &
(USI_SCL_HOLD |
{ (USI_2_WIRE &
(USI_2_WIRE &
(USI_2_WIRE &
PB2/PCINT10/
(0) : (OC1A) }
USIPOS &
USIPOS &
DDRB2) ?
PORTB2)
& DDRB2
DDRB2) |
USIPOS)
OC1AV)
SCL
0
0
0
(OC1B_ENABLE &
(USI_SHIFTOUT) :
PCIE1 & PCMSK9
{ (USI_2_WIRE &
(USI_2_WIRE &
USI_3_WIRE &
USI_3_WIRE &
PB1/PCINT9/
OC1BU/DO
USIPOS) ?
USIPOS) |
(OC1B) }
OC1BU)
PCINT9
ATtiny87/ATtiny167
0
0
0
0
0
1
0
(USISIE & USIPOS) |
(USISIE & USIPOS) |
PCINT8 -/- DI -/- SDA
PORTB0) & DDRB0)
(PCIE1 & PCMSK8)
(PCIE1 & PCMSK8)
(OC1A_ENABLE &
(USI_SHIFTOUT |
{ (USI_2_WIRE &
(USI_2_WIRE &
(USI_2_WIRE &
OC1AU/DI/SDA
PB0/IPCINT8/
(0) : (OC1A) }
USIPOS &
USIPOS &
DDRB0) ?
DDRB0) |
USIPOS)
OC1AU)
0
0
0
0
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