ATTINY167-15XD Atmel, ATTINY167-15XD Datasheet - Page 184

• Manufacturer Part Number: ATTINY167-15XD
• Description: MCU AVR 16K FLASH 15MHZ 20-TSSOP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY167-15XD

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 20-TSSOP
• Processor Series: ATTINY1x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.6.5
184
ATtiny87/ATtiny167
LIN Bit Timing Register - LINBTR
• Bit 6 - LTOERR: Frame_Time_Out Error Flag
• Bit 5 - LOVERR: Overrun Error Flag
• Bit 4 - LFERR: Framing Error Flag
• Bit 3 - LSERR: Synchronization Error Flag
• Bit 2 - LPERR: Parity Error Flag
• Bit 1 - LCERR: Checksum Error Flag
• Bit 0 - LBERR: Bit Error Flag
• Bit 7 - LDISR: Disable Bit Timing Re synchronization
Initial Value
Read/Write
Bit
– 0 = No error,
– 1 = Frame_Time_Out error.
– 0 = No error,
– 1 = Overrun error.
– 0 = No error,
– 1 = Framing error.
– 0 = No error,
– 1 = Synchronization error.
– 0 = No error,
– 1 = Parity error.
– 0 = No error,
– 1 = Checksum error.
– 0 = no error,
– 1 = Bit error.
– 0 = Bit timing re-synchronization enabled (default),
– 1 = Bit timing re-synchronization disabled.
This bit is cleared when LERR bit in LINSIR is cleared.
This bit is cleared when LERR bit in LINSIR is cleared.
This bit is cleared when LERR bit in LINSIR is cleared.
This bit is cleared when LERR bit in LINSIR is cleared.
This bit is cleared when LERR bit in LINSIR is cleared.
This bit is cleared when LERR bit in LINSIR is cleared.
This bit is cleared when LERR bit in LINSIR is cleared.
LDISR
R/W
7
0
R
6
0
-
LBT5
R/(W)
5
1
R/(W)
LBT4
4
0
R/(W)
LBT3
3
0
LBT2
R/(W)
2
0
LBT1
R/(W)
1
0
R/(W)
LBT0
0
0
7728G–AVR–06/10
LINBTR