ATTINY167-15XD Atmel, ATTINY167-15XD Datasheet - Page 36

• Manufacturer Part Number: ATTINY167-15XD
• Description: MCU AVR 16K FLASH 15MHZ 20-TSSOP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY167-15XD

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 20-TSSOP
• Processor Series: ATTINY1x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

36
ATtiny87/ATtiny167
Here is a “light” C-code of a clock switching function using automatic clock monitoring.
C Code Example
void ClockSwiching (unsigned char clk
#define CLOCK
#define CLOCK
#define CLOCK
#define CLOCK
#define WD
#define WD
unsigned char previous
}
}
// Disable interrupts
// Save the current system clock source
// Enable the new clock source
// Wait for clock validity
// Switch clock source
// Wait for effective switching
// Shut down unneeded clock source
// Re-enable interrupts
// Enable the watchdog in automatic reload mode
temp = SREG; asm ("cli");
CLKCSR = 1 << CLKCCE;
CLKCSR = CLOCK
previous
CLKSELR = ((sut << 4 ) & 0x30) | (clk
CLKCSR = 1 << CLKCCE;
CLKCSR = CLOCK
while ((CLKCSR & (1 << CLKRDY)) == 0);
CLKCSR = 1 << CLKCCE;
CLKCSR = CLOCK
while (1){
}
if (previous_clk != (clk_number & 0x0F)) {
CLKSELR = previous
CLKCSR = 1 << CLKCCE;
CLKCSR = CLOCK
SREG = temp;
WDTCSR = (1 << WDCE) | (1 << WDE);
WDTCSR = (1 << WDE ) | WD
CLKCSR = 1 << CLKCCE;
CLKCSR = WD
CLKCSR = 1 << CLKCCE;
CLKCSR = CLOCK
if ((CLKSELR & 0x0F) == (clk
_
_
ARL
2048CYCLES
_
clk = CLKSELR & 0x0F;
_
_
_
_
RECOVER
ENABLE
SWITCH
DISABLE
_
_
ENABLE
ARL
_
_
_
_
RECOVER;
ENABLE;
_
SWITCH;
DISABLE;
ENABLE;
_
_
RECOVER;
_
clk;
clk, temp;
0x05
0x02
0x04
0x01
0x06
0x07
_
2048CYCLES;
_
number & 0x0F)) break;
_
number, unsigned char sut) {
_
number & 0x0F);
7728G–AVR–06/10