EZ80F91NA050SC Zilog, EZ80F91NA050SC Datasheet - Page 102
EZ80F91NA050SC
Manufacturer Part Number
EZ80F91NA050SC
Description
IC ACCLAIM MCU 256KB 144-BGA
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F91NA050SC
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
144-LBGA
Data Bus Width
8 bit
Maximum Clock Frequency
50 MHz
Data Ram Size
16 KB
Number Of Programmable I/os
32
Number Of Timers
16 Bit
Operating Supply Voltage
3 V to 3.6 V
Mounting Style
SMD/SMT
Height
1.5 mm
Length
13 mm
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Width
13 mm
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No RoHS Version Available
Other names
269-3251
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Random Access Memory
PS019215-0910
The eZ80F91 device features 8 KB (8192 bytes) of single-port data Random Access
Memory (RAM) for general-purpose use and 8 KB of RAM for the EMAC. RAM is
enabled or disabled, and it is relocated to the top of any 64 KB page in memory. Data is
passed to and from RAM via the 8-bit data bus. On-chip RAM operates with zero wait
states. EMAC RAM is accessed via the bus arbiter and executes with zero or one Wait
states.
General-purpose RAM occupies memory addresses in the RAM Address Upper Byte reg-
ister in the range
EMAC RAM occupies memory addresses in the range
to
RAM_ADDR_U is set to
this example, RAM_ADDR_U is set to
occupies only a very small fraction of the available 16 MB address space.
When enabled, on-chip RAM assumes priority over on-chip Flash memory and any mem-
ory chip selects that is also enabled in the same address space. If an address is generated in
a range that is covered by both the RAM address space and a particular memory chip
{RAM_ADDR_U[7:0], DFFFh}.
Figure 22. Example: eZ80F91 On-Chip RAM Memory Addressing
7ADFFFh
FFFFFFh
7AFFFFh
7AC000h
7AE000h
000000h
{RAM_ADDR_U[7:0], E000h}
Location
Memory
FFh
.
Figure 22
General-Purpose
EMAC SRAM
Following a RESET, RAM is enabled when
8 KB
RAM
8 KB
7Ah
displays a memory map for on-chip RAM. In
.
Figure 22
to
{RAM_ADDR_U[7:0], FFFFh}.
{RAM_ADDR_U[7:0], C000h}
is not drawn to scale, as RAM
RAM_ADDR_U
7Ah
Product Specification
Random Access Memory
eZ80F91 MCU
93
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