EZ80F91NA050SC Zilog, EZ80F91NA050SC Datasheet - Page 238
EZ80F91NA050SC
Manufacturer Part Number
EZ80F91NA050SC
Description
IC ACCLAIM MCU 256KB 144-BGA
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F91NA050SC
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
144-LBGA
Data Bus Width
8 bit
Maximum Clock Frequency
50 MHz
Data Ram Size
16 KB
Number Of Programmable I/os
32
Number Of Timers
16 Bit
Operating Supply Voltage
3 V to 3.6 V
Mounting Style
SMD/SMT
Height
1.5 mm
Length
13 mm
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Width
13 mm
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No RoHS Version Available
Other names
269-3251
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Table 129. I
Table 130. I
PS019215-0910
Code
D8h
F8h
Bit
Reset
CPU Access
Note: W = Read only.
Bit
Position
7
[6:3]
M
[2:0]
N
Note:
Status
Second Address byte and Write bit transmitted, ACK not received.
No relevant status information, IFLG = 0.
2
2
C Status Codes (Continued)
C Clock Control Registers
If an illegal condition occurs on the I
00h
IFLG bit cleared. The I
on the I
The STP and STA bits are set to 1 at the same time to recover from the bus error. The I
then sends a START condition.
I
The I
which the I
is in MASTER mode. The Write Only I
the Read Only I2C_SR registers. See
The I
of this system clock is f
f
2
SAMP
C Clock Control Register
Value
0
0000–1111 I
000–111
). To recover from this state, the STP bit in the I
2
2
f
C_CCR register is a Write Only register. The seven LSBs control the frequency at
C clocks are derived from the system clock of the eZ80F91 device. The frequency
SAMP
supplied by the following equation:
2
C bus.
W
2
7
0
C bus is sampled and the frequency of the I
=
Description
Reserved.
I
2
2
f
C clock divider scalar value.
C clock divider exponent.
SCLK
2
W
6
0
N
2
SCK
C then returns to an idle state. No STOP condition is transmitted
. The I
W
5
0
(I2C_CCR = 00CCh)
2
C bus is sampled by the I
W
4
0
2
Table
C bus, the bus error state is entered (status code
2
C_CCR registers share the same I/O addresses as
130.
W
3
0
2
W
2
0
C_CTL register must be set and the
2
C clock line (SCL) when the I
W
2
1
0
C block at the frequency
Product Specification
W
0
0
I
2
C Serial I/O Interface
2
2
C
C
229
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