EZ80F91NA050SC Zilog, EZ80F91NA050SC Datasheet - Page 205
![IC ACCLAIM MCU 256KB 144-BGA](/photos/12/15/121558/269-144-bga_sml.jpg)
EZ80F91NA050SC
Manufacturer Part Number
EZ80F91NA050SC
Description
IC ACCLAIM MCU 256KB 144-BGA
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F91NA050SC
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
144-LBGA
Data Bus Width
8 bit
Maximum Clock Frequency
50 MHz
Data Ram Size
16 KB
Number Of Programmable I/os
32
Number Of Timers
16 Bit
Operating Supply Voltage
3 V to 3.6 V
Mounting Style
SMD/SMT
Height
1.5 mm
Length
13 mm
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Width
13 mm
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No RoHS Version Available
Other names
269-3251
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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- Download datasheet (3Mb)
PS019215-0910
UART_TxD
Baud Rate
Transmit
Receive
IR_TxD
7-clock
Clock
delay
IrDA specifications. The UART must be enabled to use the endec. For more information on
the UART and its BRG, see
The data to be transmitted via the IR transceiver is the data sent to UART0. The UART
transmit signal, TxD, and Baud Rate Clock are used by the endec to generate the
modulation signal, IR_TxD, that drives the infrared transceiver. Each UART bit is 16
clocks wide. If the data to be transmitted is a logical 1 (High), the IR_TxD signal remains
Low (0) for the full 16-clock period. If the data to be transmitted is a logical 0, a 3-clock
High (1) pulse is output following a 7-clock Low (0) period. Following the 3-clock High
pulse, a 6-clock Low pulse completes the full 16-clock data period. Data transmission is
displayed in
by clearing the IR_RxEN bit in the IR_CTL reg to 0 to prevent transmitter-to-receiver
crosstalk.
Data received from the IR transceiver via the IR_RxD signal is decoded by the endec and
passed to the UART. The IR_RxEN bit in the IR_CTL register must be set to enable the
receiver decoder. The IrDA serial infrared (SIR) data format uses half duplex communica-
tion. Therefore, the UART must not be allowed to transmit while the receiver decoder is
enabled. The UART Baud Rate Clock is used by the endec to generate the demodulated
signal, RxD, that drives the UART. Each UART bit is 16 clocks wide. If the data to be
received is a logical 1 (High), the IR_RxD signal remains High (1) for the full 16-clock
Start Bit = 0
16-clock
period
3-clock
pulse
Figure
Figure 38. Infrared Data Transmission
38. During data transmission, the IR receive function must be disabled
Data Bit 0 = 1
Universal Asynchronous Receiver/Transmitter
Data Bit 1 = 0
Data Bit 2 = 1
Product Specification
Infrared Encoder/Decoder
Data Bit 3 = 1
on page 175.
196
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