EZ80F91NA050SC Zilog, EZ80F91NA050SC Datasheet - Page 314

• Manufacturer Part Number: EZ80F91NA050SC
• Description: IC ACCLAIM MCU 256KB 144-BGA
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91NA050SC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-LBGA
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 50 MHz
• Data Ram Size: 16 KB
• Number Of Programmable I/os: 32
• Number Of Timers: 16 Bit
• Operating Supply Voltage: 3 V to 3.6 V
• Mounting Style: SMD/SMT
• Height: 1.5 mm
• Length: 13 mm
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Width: 13 mm
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No RoHS Version Available
• Other names: 269-3251

Table 187. EMAC Transmit Pause Timer Value Register—Low Byte
Table 188.
PS019215-0910
Bit 
Position
[7:0]
EMAC_STAD_x
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit 
Position
[7:0]
EMAC_TPTV_L
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit 
Position
[7:0]
EMAC_TPTV_H
EMAC Transmit Pause Timer Value
EMAC Transmit Pause Timer Value Register—Low and High Bytes
The Low and High bytes of the EMAC Transmit Pause Timer Value Register are inserted
into outgoing pause control frames. See
Value
00h–FFh This 48-bit station address comprises {EMAC_STAD_5,
Value
00h–FFh The 16-bit value, {EMAC_TPTV_H, EMAC_TPTV_L}, is
Value
00h–FFh The 16-bit value, {EMAC_TPTV_H, EMAC_TPTV_L}, is
R/W
R/W
Description
inserted into outgoing pause control frames as the pause
timer value upon asserting TPCF.
Description
EMAC_STAD_4, EMAC_STAD_3, EMAC_STAD_2,
EMAC_STAD_1, EMAC_STAD_0}.
Description
inserted into outgoing pause control frames as the pause
timer value upon asserting TPCF.
7
0
7
0
R/W
R/W
6
0
6
0
R/W
R/W
5
0
5
0
R/W
R/W
Register
4
0
4
0
Table 187
R/W
R/W
3
0
3
0
—High Byte
and
R/W
R/W
2
0
2
0
Table
(EMAC_TPTV_L = 002Bh)
Ethernet Media Access Controller
R/W
R/W
188.
1
0
1
0
(EMAC_TPTV_H = 002Ch)
Product Specification
R/W
R/W
0
0
0
0
305