EZ80F91NA050SC Zilog, EZ80F91NA050SC Datasheet - Page 223
![IC ACCLAIM MCU 256KB 144-BGA](/photos/12/15/121558/269-144-bga_sml.jpg)
EZ80F91NA050SC
Manufacturer Part Number
EZ80F91NA050SC
Description
IC ACCLAIM MCU 256KB 144-BGA
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F91NA050SC
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
144-LBGA
Data Bus Width
8 bit
Maximum Clock Frequency
50 MHz
Data Ram Size
16 KB
Number Of Programmable I/os
32
Number Of Timers
16 Bit
Operating Supply Voltage
3 V to 3.6 V
Mounting Style
SMD/SMT
Height
1.5 mm
Length
13 mm
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Width
13 mm
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No RoHS Version Available
Other names
269-3251
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 223 of 384
- Download datasheet (3Mb)
PS019215-0910
Clock Synchronization
All masters generate their own clocks on the SCL line to transfer messages on the I
Data is only valid during the High period of each clock.
Clock synchronization is performed using the wired AND connection of the I
to the SCL line, meaning that a High-to-Low transition on the SCL line causes the relevant
devices to start counting from their Low period. When a device clock goes Low, it holds
the SCL line in that state until the clock High state is reached. See
The Low-to-High transition of this clock, however, cannot change the state of the SCL
line if another clock is still within its Low period. The SCL line is held Low by the device
with the longest Low period. Devices with shorter Low periods enter a High wait state
during this time.
When all devices count off the Low period, the clock line is released and goes High. There
is no difference between the device clocks and the state of the SCL line; all of the devices
start counting the High periods. The first device to complete its High period again pulls
the SCL line Low. In this way, a synchronized SCL clock is generated with its Low period
determined by the device with the longest clock Low period, and its High period
determined by the device with the shortest clock High period.
by Transmitter
Data Output
Data Output
from Master
by Receiver
SCL Signal
START Condition
S
Clock Pulse for Acknowledge
Figure 46. I
MSB
1
1
2
2
C Acknowledge
8
9
Product Specification
Figure 47
I
2
C Serial I/O Interface
2
on page 215.
C interfaces
2
C bus.
214
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